公开(公告)号：US3859637A

公开(公告)日：1975-01-07

申请号：US37461673

申请日：1973-06-28

Applicant: IBM

Inventor： PLATT STEVEN ,  POMERANZ JEHOSHUA N ,  TEWARSON DINESH K

IPC: G11C5/00 ,  G11C8/18 ,  G11C11/34 ,  G11C11/415 ,  G11C11/417 ,  G11C11/418 ,  H03M7/00 ,  G11C11/40

CPC classification number: G11C11/418 ,  G11C5/00 ,  G11C8/18 ,  G11C11/415 ,  G11C11/417 ,  H03M7/00

Abstract: A monolithic semiconductor array of bi-level powered memory cells is provided with a number of on-chip row and column primary latching circuits. The primary latching circuits allow for the down-powering of the on-chip row and column address decoders after a particular chip and a particular storage cell on the chip have been selected by a respective address signal and a set signal. An auxiliary latching circuit, substantially identical to each of the aforesaid primary latching circuits, also is provided on-chip and receives the same set signal as does each primary latching circuit. The primary latching circuits and the auxiliary latching circuit are ''''set'''' substantially simultaneously by the set signal. The setting of the auxiliary latching circuit initiates a signal which downpowers each of the on-chip address decoders. Means are also provided on-chip for resetting each of the selected primary and the auxiliary latching circuits upon the termination of the chip select signal.

Abstract translation: 双层电源存储单元的单片半导体阵列具有多个片上行和列主要锁存电路。 主要锁存电路允许在芯片上的特定芯片和芯片上的特定存储单元被相应的地址信号和设置信号选择之后片上行和列地址解码器的下电。 基本上与上述主锁存电路基本相同的辅助锁存电路也被提供在片上并且接收与每个主锁存电路相同的设置信号。 主锁存电路和辅助锁存电路通过设定信号基本上同时设定。 辅助锁存电路的设置启动一个使每个片上地址解码器下降的信号。 在芯片选择信号终止时，芯片还提供用于复位所选择的主要和辅助锁存电路中的每一个的装置。