公开(公告)号：US3676704A

公开(公告)日：1972-07-11

申请号：US3676704D

申请日：1970-12-29

Applicant: IBM

Inventor： DONOFRIO NICHOLAS M ,  POMERANZ JEHOSHUA N

IPC: G11C11/414 ,  G11C11/416 ,  H03K5/02 ,  H03K5/20

CPC classification number: H03K5/02 ,  G11C11/416

Abstract: This specification describes a sense amplifier/bit driver circuit for a monolithic memory storage cell with a double ended output. The sense amplifier consists of two shunt feedback amplifiers connected differentially across the double ended output of the storage cell. There is a resistive connection between the outputs of the two shunt feedback amplifiers to make each input of the two shunt feedback amplifiers relatively insensitive to large changes at the other input. The bit driver for the circuit contains two current switch circuits for controlling the potential at each end of the double ended output of the storage cell. These current switch circuits are crosscoupled by a transistor which eliminates the need for inverting one of the control pulses to the bit driver.

Abstract translation: 该规范描述了具有双端输出的单片存储器存储单元的读出放大器/位驱动器电路。 读出放大器由两个分流反馈放大器组成，分别跨接在存储单元的双端输出端。 两个并联反馈放大器的输出之间存在电阻连接，以使两个并联反馈放大器的每个输入对另一个输入端的大变化相对不敏感。 电路的位驱动器包含两个电流开关电路，用于控制存储单元的双端输出的每端的电位。 这些电流开关电路通过晶体管交叉耦合，这消除了将控制脉冲之一反转到位驱动器的需要。

公开(公告)号：US3537078A

公开(公告)日：1970-10-27

申请号：US3537078D

申请日：1968-07-11

Applicant: IBM

Inventor： POMERANZ JEHOSHUA N

IPC: G11C11/411 ,  H03K3/286 ,  G11C11/36

CPC classification number: G11C11/4116

公开(公告)号：US3656004A

公开(公告)日：1972-04-11

申请号：US3656004D

申请日：1970-09-28

Applicant: IBM

Inventor： KEMERER DOUGLAS W ,  POMERANZ JEHOSHUA N

IPC: H03K17/042 ,  H03K17/60 ,  H03K17/66 ,  H03K17/00

CPC classification number: H03K17/04213 ,  H03K17/602 ,  H03K17/666

Abstract: This specification discloses a bipolar driver which will charge a capacitive load to substantially the potential supplied to the driver. The driver includes two transistors that couple the load to a source of potential. One transistor is connected in shunt with the load while the other transistor is connected in series with the load and the source of potential. The shunt-connected transistor is used to discharge the capacitive load while the serially connected transistor is used to charge the capacitive load with charge from the source of potential. To allow the capacitive load to be charged to the full potential of the source, the driver includes circuitry which decouples the base of the serially connected transistor from the source of potential and drives the transistor with charge accumulated in the base-toemitter junction of the transistor so that the serially connected transistor will not be turned off until the potential across the capacitive load reaches the potential of the driving source.

Abstract translation: 本说明书公开了一种双极驱动器，其将对容性负载充电至基本上提供给驱动器的电位。 驱动器包括将负载耦合到电位源的两个晶体管。 一个晶体管与负载分流连接，而另一个晶体管与负载和电位源串联连接。 分流连接的晶体管用于放电容性负载，而串联连接的晶体管用于从电势源的电荷对电容负载充电。 为了使容性负载被充电到电源的全部电位，驱动器包括使串联连接的晶体管的基极与电位源分离的电路，并驱动晶体管，其中电荷累积在基极 - 发射极结中 晶体管，使得串联的晶体管将不会被截止，直到电容负载两端的电位达到驱动源的电位。

公开(公告)号：US3859637A

公开(公告)日：1975-01-07

申请号：US37461673

申请日：1973-06-28

Applicant: IBM

Inventor： PLATT STEVEN ,  POMERANZ JEHOSHUA N ,  TEWARSON DINESH K

IPC: G11C5/00 ,  G11C8/18 ,  G11C11/34 ,  G11C11/415 ,  G11C11/417 ,  G11C11/418 ,  H03M7/00 ,  G11C11/40

CPC classification number: G11C11/418 ,  G11C5/00 ,  G11C8/18 ,  G11C11/415 ,  G11C11/417 ,  H03M7/00

Abstract: A monolithic semiconductor array of bi-level powered memory cells is provided with a number of on-chip row and column primary latching circuits. The primary latching circuits allow for the down-powering of the on-chip row and column address decoders after a particular chip and a particular storage cell on the chip have been selected by a respective address signal and a set signal. An auxiliary latching circuit, substantially identical to each of the aforesaid primary latching circuits, also is provided on-chip and receives the same set signal as does each primary latching circuit. The primary latching circuits and the auxiliary latching circuit are ''''set'''' substantially simultaneously by the set signal. The setting of the auxiliary latching circuit initiates a signal which downpowers each of the on-chip address decoders. Means are also provided on-chip for resetting each of the selected primary and the auxiliary latching circuits upon the termination of the chip select signal.

Abstract translation: 双层电源存储单元的单片半导体阵列具有多个片上行和列主要锁存电路。 主要锁存电路允许在芯片上的特定芯片和芯片上的特定存储单元被相应的地址信号和设置信号选择之后片上行和列地址解码器的下电。 基本上与上述主锁存电路基本相同的辅助锁存电路也被提供在片上并且接收与每个主锁存电路相同的设置信号。 主锁存电路和辅助锁存电路通过设定信号基本上同时设定。 辅助锁存电路的设置启动一个使每个片上地址解码器下降的信号。 在芯片选择信号终止时，芯片还提供用于复位所选择的主要和辅助锁存电路中的每一个的装置。