公开(公告)号：US20240114614A1

公开(公告)日：2024-04-04

申请号：US17956544

申请日：2022-09-29

Applicant: ICP Technology Co., LTD. ,  SENTEC E&E CO., LTD.

Inventor： HO-CHIEH YU ,  CHEN-CHENG-LUNG LIAO ,  CHUN-YU LIN ,  JASON AN CHENG HUANG ,  CHIH-CHUAN LIANG ,  KUN-TZU CHEN ,  NAI-HIS HU ,  LIANG-YO CHEN

IPC: H05K1/02 ,  H05K1/03 ,  H05K3/00

CPC classification number: H05K1/021 ,  H05K1/0206 ,  H05K1/0306 ,  H05K3/0061 ,  H05K2201/10166

Abstract: Disclosed is a thermal conduction-electrical conduction isolated circuit board with a ceramic substrate and a power transistor embedded, mainly comprising: a dielectric material layer, a heat-dissipating ceramic block, a securing portion, a stepped metal electrode layer, a power transistor, and a dielectric material packaging, wherein a via hole is formed in the dielectric material layer, the heat-dissipating ceramic block is correspondingly embedded in the via hole, the heat-dissipating ceramic block has a thermal conductivity higher than that of the dielectric material layer and a thickness less than that of the dielectric material layer, the stepped metal electrode layer conducts electricity and heat for the power transistor, the dielectric material packaging is configured to partially expose the source connecting pin, drain connecting pin, and gate connecting pin of the encapsulated stepped metal electrode layer.

公开(公告)号：US20250132233A1

公开(公告)日：2025-04-24

申请号：US18381598

申请日：2023-10-18

Applicant: ICP TECHNOLOGY CO., LTD. ,  SENTEC E&E CO., LTD.

Inventor： HO-CHIEH YU ,  CHEN-CHENG-LUNG LIAO ,  CHUN-YU LIN ,  JASON AN CHENG HUANG ,  Liang-Yo CHEN

IPC: H01L23/495 ,  H01L23/00 ,  H01L25/065

Abstract: Disclosed are a heat-electricity discrete power module with two-way heat-dissipation ceramic substrates and a manufacturing method of the same, including: two double-sided metal-clad ceramic substrates, a power transistor die, and an insulation sealant; each double-sided metal-clad ceramic substrate including a ceramic insulation layer, a three-dimensional conductive layer formed on the first ceramic insulation layer and facing the opposite three-dimensional conductive layer to constitute an electrical circuit, and a thermally-conductive metallic layer opposite and insulated from the three-dimensional conductive layer, respectively; electrodes of each power transistor die are electrically conductively connected to the three-dimensional conductive layer, and their upper and lower surfaces are thermally conductively connected to respective three-dimensional conductive layers; circuit components are additionally mounted on the three-dimensional conductive layers; at least one conductive post is formed between the circuits of respective three-dimensional conductive layers; the power transistor die and conductive post are completely encapsulated by the insulation sealant.

公开(公告)号：US20230378145A1

公开(公告)日：2023-11-23

申请号：US18197607

申请日：2023-05-15

Applicant: ICP TECHNOLOGY CO., LTD. ,  Sentec Green Energy Technology Co., Ltd.

Inventor： HO-CHIEH YU ,  CHEN-CHENG-LUNG LIAO ,  CHUN-YU LIN ,  JASON AN CHENG HUANG ,  CHIH-CHUAN LIANG ,  KUN-TZU CHEN ,  NAI-HIS HU

IPC: H01L25/16 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L25/16 ,  H01L23/49838 ,  H01L24/05 ,  H01L24/06 ,  H01L2224/05552 ,  H01L2224/05553 ,  H01L2224/06051 ,  H01L2224/06155

Abstract: Disclosed is a flip-chip packaged power transistor module having a built-in gate driver, for outputting a high-power signal of at least tens of amperes, the module including at least one power transistor die which has an active side where at least one source pin, at least one drain pin and at least one gate pin are exposed; a ceramic substrate body which has a conducting junction side and a heat spreading side, a minimal spacing of the gate bonding pad from at least one of the source bonding pad or the drain bonding pad being less than 500 μm, whereby parasitic inductance generated therebetween is reduced; at least one gate driver which has at least one gate pin configured to be soldered to the gate bonding pad, and at least one gate drive pin which corresponds to the gate pin and is configured to be soldered to the drive bonding pad.