公开(公告)号：US20240039541A1

公开(公告)日：2024-02-01

申请号：US17815368

申请日：2022-07-27

Applicant: IMEC VZW

Inventor： Quentin Paul Herr ,  Anna Yurievna Herr

IPC: H03K19/23 ,  H03K19/17736 ,  H01L39/24

CPC classification number: H03K19/23 ,  H03K19/1774 ,  H01L39/2493

Abstract: Josephson junction based logic devices and methods for their use are described. An example Josephson junction based logic device includes a two-input OR/AND (OA2) gate. The OA2 gate includes a first input node inductively coupled to a first input source and a second input node inductively coupled to a second input source. The first and second input sources are configured to provide single-flux-quantum (SFQ) pulses. The OA2 gate also includes first plurality of inductors coupled between the first input node and one of: a first output node or a second output node. The OA2 gate additionally includes a second plurality of inductors coupled between the second input node and one of: the first or the second output nodes. The OA2 gate also includes Josephson junctions coupled between a common node and one of: the first or the second input node, or the first or the second output node.

公开(公告)号：US20240038298A1

公开(公告)日：2024-02-01

申请号：US17815358

申请日：2022-07-27

Applicant: IMEC VZW

Inventor： Henry Luo ,  Anna Yurievna Herr ,  Quentin Paul Herr

IPC: G11C11/44

CPC classification number: G11C11/44

Abstract: Josephson junction based memory devices and methods for their use are described herein. An example Josephson junction based memory device includes a plurality of superconducting loops. Each superconducting loop includes at least one Josephson junction. The plurality of superconducting loops are electrically coupled. The plurality of superconducting loops include a plurality of input loops, a plurality of readout loops, and at least one shared loop. The plurality of superconducting loops are configured to store or annihilate magnetic flux quanta in one or more of the superconducting loops in response to a combination of control signals and single flux quantum (SFQ) pulses.

公开(公告)号：US12206413B2

公开(公告)日：2025-01-21

申请号：US17815368

申请日：2022-07-27

Applicant: IMEC VZW

Inventor： Quentin Paul Herr ,  Anna Yurievna Herr

IPC: H03K19/195 ,  H03K19/17736 ,  H03K19/23 ,  H10N60/01

Abstract: Josephson junction based logic devices and methods for their use are described. An example Josephson junction based logic device includes a two-input OR/AND (OA2) gate. The OA2 gate includes a first input node inductively coupled to a first input source and a second input node inductively coupled to a second input source. The first and second input sources are configured to provide single-flux-quantum (SFQ) pulses. The OA2 gate also includes first plurality of inductors coupled between the first input node and one of: a first output node or a second output node. The OA2 gate additionally includes a second plurality of inductors coupled between the second input node and one of: the first or the second output nodes. The OA2 gate also includes Josephson junctions coupled between a common node and one of: the first or the second input node, or the first or the second output node.

公开(公告)号：US12094530B2

公开(公告)日：2024-09-17

申请号：US17815358

申请日：2022-07-27

Applicant: IMEC VZW

Inventor： Henry Luo ,  Anna Yurievna Herr ,  Quentin Paul Herr

IPC: G11C11/44

CPC classification number: G11C11/44

Abstract: Josephson junction based memory devices and methods for their use are described herein. An example Josephson junction based memory device includes a plurality of superconducting loops. Each superconducting loop includes at least one Josephson junction. The plurality of superconducting loops are electrically coupled. The plurality of superconducting loops include a plurality of input loops, a plurality of readout loops, and at least one shared loop. The plurality of superconducting loops are configured to store or annihilate magnetic flux quanta in one or more of the superconducting loops in response to a combination of control signals and single flux quantum (SFQ) pulses.