公开(公告)号：US20250125291A1

公开(公告)日：2025-04-17

申请号：US18685402

申请日：2023-02-21

Applicant: MICLEDI MICRODISPLAYS BV ,  IMEC VZW

Inventor： Emmanuel LE BOULBAR ,  Soeren STEUDEL ,  Johan VERTOMMEN ,  Robert MILLER ,  Joeri DE VOS ,  Stefaan VAN HUYLENBROECK ,  Eric BEYNE ,  Liesbeth WITTERS

IPC: H01L23/00

Abstract: A semiconductor product is provided. The semiconductor product comprises a first wafer (21) comprising a first active pad array (21a), and at least a second wafer (22) comprising at least a second active pad array (22a). In this context, the first wafer (21) and the at least one second wafer (22) are bonded together. In addition to this, the first wafer (21) and/or the at least one second wafer (22) comprises a transition area (23) being directly adjacent to the first active pad array (21a) and/or the at least one second active pad array (22a).

公开(公告)号：US20230170297A1

公开(公告)日：2023-06-01

申请号：US17991255

申请日：2022-11-21

Applicant: IMEC VZW

Inventor： Shih-Hung CHEN ,  Eric BEYNE ,  Geert VAN DER PLAS

IPC: H01L23/522 ,  H01L27/02 ,  H01L27/105 ,  H01L23/492 ,  H01L23/60 ,  H01L23/00

CPC classification number: H01L23/5226 ,  H01L23/60 ,  H01L23/4926 ,  H01L24/02 ,  H01L27/105 ,  H01L27/0255 ,  H01L27/0259 ,  H01L27/0292 ,  H01L2224/02373

Abstract: A semiconductor component, for example an integrated circuit chip, including a semiconductor substrate having active devices at the front side thereof and I/O terminals at the back side of the component, is provided. In one aspect, the terminals are connected to the active devices through TSV connections and buried rails in an area of the substrate that is separate from the area in which the active devices are located. The I/O TSV connections are located in a floating well of the substrate that is separated from the rest of the substrate by a second well formed of material of the opposite conductivity type compared to the material of the floating well. The second well includes at least one contact configured to be coupled to a voltage that is suitable for reverse-biasing the junction between the floating well and the second well. A small capacitance is placed in series with the large parasitic capacitance generated by a thin dielectric liner that isolates the I/O TSVs and I/O rails from the substrate, thereby mitigating the negative effect of the large parasitic capacitance. Additional contacts and conductors can be provided which are configured to create an ESD protection circuit for protecting the I/O TSVs and the I/O rails from electrostatic discharges.

公开(公告)号：US20220189830A1

公开(公告)日：2022-06-16

申请号：US17550508

申请日：2021-12-14

Applicant: MICLEDI MICRODISPLAYS BV ,  IMEC VZW

Inventor： Eric BEYNE ,  Robert MILLER ,  Kenneth June REBIBIS ,  Soeren STEUDEL ,  Johan VERTOMMEN

IPC: H01L21/66 ,  H01L21/78 ,  G01N21/95

Abstract: A method is provided to produce dies for a wafer reconstitution. The method comprises steps of inspecting an epitaxial wafer to detect one or more defects, overlaying a dicing scheme on the epitaxial wafer with the detected defects, classifying the dies in the dicing scheme as good dies or bad dies, and dicing the good dies and transferring the good dies onto a carrier wafer or a target wafer to wafer reconstitution.