公开(公告)号：US20150069529A1

公开(公告)日：2015-03-12

申请号：US14478817

申请日：2014-09-05

Applicant: IMEC VZW

Inventor： Shih-Hung CHEN ,  Dimitri LlNTEN

IPC: H01L23/00 ,  H01L29/78

CPC classification number: H01L23/564 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/0692 ,  H01L29/78 ,  H01L29/87 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The disclosed technology generally relates to electrostatic discharge protection devices that protect circuits from transient electrical events and more particularly to low-voltage triggered silicon-controlled rectifier devices implemented using a bulk fin field-effect transistor technology. In one aspect, an electrostatic discharge protection device comprises a low-voltage triggered silicon-controlled rectifier having an embedded grounded-gate n-channel metal oxide semiconductor structure implemented as a bulk fin field-effect transistor having a plurality of fin structures. The fin structures direct current from an avalanche zone to a gate formed over the fin structure. The electrostatic discharge protection device has a higher trigger current and a lower leakage current than a similar device having a planar embedded grounded-gate n-channel metal oxide semiconductor structure because the current flow is restricted by the fin structures.

Abstract translation: 所公开的技术通常涉及保护电路免受瞬态电事件的静电放电保护装置，更具体地涉及使用体翅片场效应晶体管技术实现的低电压触发的可控硅整流器件。 一方面，静电放电保护装置包括具有嵌入的接地栅极n沟道金属氧化物半导体结构的低电压触发的可控硅整流器，其被实现为具有多个鳍结构的体翅片场效应晶体管。 翅片结构将电流从雪崩区域引导到形成在鳍结构上的栅极。 与具有平面嵌入式接地栅极n沟道金属氧化物半导体结构的类似器件相比，静电放电保护器具有较高的触发电流和较低的漏电流，因为电流被翅片结构限制。

公开(公告)号：US20230170297A1

公开(公告)日：2023-06-01

申请号：US17991255

申请日：2022-11-21

Applicant: IMEC VZW

Inventor： Shih-Hung CHEN ,  Eric BEYNE ,  Geert VAN DER PLAS

IPC: H01L23/522 ,  H01L27/02 ,  H01L27/105 ,  H01L23/492 ,  H01L23/60 ,  H01L23/00

CPC classification number: H01L23/5226 ,  H01L23/60 ,  H01L23/4926 ,  H01L24/02 ,  H01L27/105 ,  H01L27/0255 ,  H01L27/0259 ,  H01L27/0292 ,  H01L2224/02373

Abstract: A semiconductor component, for example an integrated circuit chip, including a semiconductor substrate having active devices at the front side thereof and I/O terminals at the back side of the component, is provided. In one aspect, the terminals are connected to the active devices through TSV connections and buried rails in an area of the substrate that is separate from the area in which the active devices are located. The I/O TSV connections are located in a floating well of the substrate that is separated from the rest of the substrate by a second well formed of material of the opposite conductivity type compared to the material of the floating well. The second well includes at least one contact configured to be coupled to a voltage that is suitable for reverse-biasing the junction between the floating well and the second well. A small capacitance is placed in series with the large parasitic capacitance generated by a thin dielectric liner that isolates the I/O TSVs and I/O rails from the substrate, thereby mitigating the negative effect of the large parasitic capacitance. Additional contacts and conductors can be provided which are configured to create an ESD protection circuit for protecting the I/O TSVs and the I/O rails from electrostatic discharges.