公开(公告)号：US20230178554A1

公开(公告)日：2023-06-08

申请号：US18060785

申请日：2022-12-01

Applicant: IMEC VZW

Inventor： Bilal Chehab ,  Pieter Schuddinck ,  Julien Ryckaert ,  Pieter Weckx

IPC: H01L27/092 ,  H01L23/528 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775

CPC classification number: H01L27/0922 ,  H01L23/528 ,  H01L29/0673 ,  H01L29/775 ,  H01L29/42392

Abstract: Example embodiments relate to complementary field-effect transistor (CFET) devices. An example CFET device includes a bottom FET device. The bottom FET device includes a bottom channel nanostructure having a first side surface oriented in a first direction. The bottom FET device also includes a second side surface oriented in a second direction opposite the first direction. Further, the bottom FET device includes a bottom gate electrode configured to define a tri-gate or a gate-all-around with respect to the bottom channel nanostructure. The bottom gate electrode includes a side gate portion arranged along the first side surface of the bottom channel nanostructure. The CFET device also includes a top FET device stacked on the bottom FET device. The top FET device includes channel layers, a gate electrode, and gate prongs. Additionally, the CFET device includes a top gate contact via. Further, the CFET device includes a bottom gate contact via.

公开(公告)号：US20240429274A1

公开(公告)日：2024-12-26

申请号：US18753824

申请日：2024-06-25

Applicant: IMEC VZW

Inventor： Geert Hellings ,  Pieter Schuddinck

IPC: H01L29/06 ,  H01L27/092 ,  H01L29/417 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

Abstract: Provided herein is a nanosheet device that includes a first and a second transistor structure, each comprising a respective source region, drain region, and channel region extending between the respective source and drain regions, a dielectric wall, a gate structure, and a gate spacer, wherein the channel region of the first transistor structure includes a first set of vertically stacked channel layers, wherein each channel layer of the first set of vertically stacked channel layers has an inward facing surface contacting a first side surface of the dielectric wall, and wherein the channel region of the second transistor structure includes a second set of vertically stacked channel layers, and wherein each channel layer of the second set of vertically stacked channel layers has an inward facing surface contacting a second side surface, opposite to the first side surface, of the dielectric wall

公开(公告)号：US20240204080A1

公开(公告)日：2024-06-20

申请号：US18538879

申请日：2023-12-13

Applicant: IMEC VZW ,  Katholieke Universiteit Leuven

Inventor： Boon Teik Chan ,  Hsiao-Hsuan Liu ,  Pieter Schuddinck

IPC: H01L29/66 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/66545 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823871 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/41775 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

Abstract: A method for forming a semiconductor device is provided. The method includes: forming, over a substrate, a stacked transistor structure comprising: a bottom channel structure and a top channel structure, a gate structure extending across the bottom and top channel structures, a first and a second bottom S/D structure on the bottom channel structure, and a first and a second top S/D structure on the top channel structure; forming a first and a second bottom S/D contact on the first and the second bottom S/D structures; forming a contact isolation layer capping the first and second bottom S/D contacts, and covering the capped first and second bottom S/D contacts with an ILD layer; forming a first contact trench; forming a second contact trench; and forming a first top S/D contact.

公开(公告)号：US09601379B1

公开(公告)日：2017-03-21

申请号：US14757996

申请日：2015-12-23

Applicant: GLOBALFOUNDRIES Inc. ,  IMEC VZW

Inventor： Bartlomiej Jan Pawlak ,  Dmitry Yakimets ,  Pieter Schuddinck

IPC: H01L29/06 ,  H01L21/8234 ,  H01L21/265 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/308 ,  H01L29/423 ,  H01L23/532 ,  H01L27/088

CPC classification number: H01L29/0673 ,  B82Y10/00 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/53242 ,  H01L23/53257 ,  H01L29/0653 ,  H01L29/41725 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775

Abstract: In one example, the method disclosed herein includes, among other things, forming a sacrificial structure around a plurality of stacked substantially un-doped nanowires at a location that corresponds to the channel region of the device, performing a selective etching process through a cavity to remove a second plurality of nanowires from the channel region and the source/drain regions of the device while leaving a first plurality of nanowires in position, and forming a metal conductive source/drain contact structure in each of the source/drain regions, wherein each of the metal conductive source/drain contact structures is positioned all around the first plurality of nanowires positioned in the source/drain regions.