公开(公告)号：US20250165793A1

公开(公告)日：2025-05-22

申请号：US18393464

申请日：2023-12-21

Applicant: Industrial Technology Research Institute

Inventor： Chia-Hsiang Yang ,  Shih-Hao Chen ,  Chih-Wei Liu

IPC: G06N3/092

Abstract: An algorithm method for deep reinforcement learning includes initializing an environment and a model; executing an experience collection process and a network update process in parallel, and determining whether the experience collection process and the network update process have reached a termination condition; and continuing executing the experience collection process and the network update process in parallel in response to neither of the experience collection process and the network update processes has met the termination conditions; and stopping executing the experience collection process and the network update process in response to one of the experience collection processes and the network update process having met the termination conditions. The experience collection process includes obtaining a current state of the environment; calculating to determine the current action based on the current observation values according to a current policy of the model; and returning the current action to the environment.

公开(公告)号：US20240220210A1

公开(公告)日：2024-07-04

申请号：US18152170

申请日：2023-01-10

Applicant: Industrial Technology Research Institute

Inventor： Chia-Hsiang Yang ,  Liang-Hsin Lin ,  Yu-Ling Kang ,  Yu-Hui Lin ,  Chih-Ming Lai

IPC: G06F7/72 ,  G06F5/01

CPC classification number: G06F7/729 ,  G06F5/01

Abstract: A modulo divider and a modulo division operation method for binary data are provided, including: converting a first variant and a second variant to a variant set according to a first mapping table; generating a fifth variant and a sixth variant according to the variant set; generating a seventh variant and an eighth variant according to the variant set; updating the first variant according to one of the fifth variant and the sixth variant and updating the second variant according to the other one of the fifth variant and the sixth variant; updating the third variant according to one of the seventh variant and the eighth variant and updating the fourth variant according to the other one of the seventh variant and the eighth variant; and outputting the third variant as a result of a modulo division operation in response to determining the updating of the third variant being finished.

公开(公告)号：US11829731B2

公开(公告)日：2023-11-28

申请号：US17562793

申请日：2021-12-27

Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE

Inventor： Chia-Hsiang Yang ,  Liang-Hsin Lin ,  Yu-Ling Kang ,  Li-Chi Su

IPC: G06F7/72

CPC classification number: G06F7/722 ,  G06F7/728

Abstract: A modular multiplication circuit includes a main operation circuit, a look-up table, and an addition unit. The main operation circuit updates a sum value and a carry value according to 2iA corresponding to a first operation value A and m bits of a second operation value B currently under operation, m is a positive integer, i is from 0 to m−1. The look-up table records values related to a modulus, and selects one of the values as a look-up table output value according to the sum value. The addition unit updates the sum value and the carry value according to the look-up table output value and outputs the updated sum value and the updated carry value to the main operation circuit. The modular multiplication circuit updates the sum value and the carry value in a recursive manner by using m different bits of the second operation value B.

公开(公告)号：US20240012873A1

公开(公告)日：2024-01-11

申请号：US18077126

申请日：2022-12-07

Applicant: Industrial Technology Research Institute

Inventor： Chia-Hsiang Yang ,  Chen-Chien Kao ,  Chao-Hung Chen

IPC: G06F17/16 ,  G06F17/14

CPC classification number: G06F17/16 ,  G06F17/145 ,  G06F17/147

Abstract: An electronic device and a method for accelerating canonical polyadic (CP) decomposition are provided. The method includes: performing at least one of a Walsh-Hadamard transform (WHT) operation and a discrete cosine transform (DCT) operation on a first factor matrix, a second factor matrix, and a tensor respectively to update the first factor matrix, the second factor matrix and the tensor; sampling the updated first factor matrix and the updated second factor matrix to generate a first sampled matrix, and sampling an unfolded matrix of the updated tensor to generate a second sampled matrix; solving a least square problem of the first sampled matrix and the second sampled matrix to generate or update a third factor matrix of the tensor so as to update multiple components of the tensor; and outputting multiple components after an updating of multiple components is finished.