公开(公告)号：US09240248B2

公开(公告)日：2016-01-19

申请号：US14473872

申请日：2014-08-29

Applicant: INPHI CORPORATION

Inventor： Hamid Reza Rategh ,  David T. Wang ,  Lawrence Tse

IPC: G11C11/34 ,  G11C29/04 ,  G11C8/06 ,  G11C5/04 ,  G11C29/44 ,  G11C7/10 ,  G11C11/413 ,  G11C16/08 ,  G11C29/00 ,  G11C29/08

CPC classification number: G11C29/04 ,  G11C5/04 ,  G11C7/1012 ,  G11C8/06 ,  G11C11/413 ,  G11C16/08 ,  G11C29/08 ,  G11C29/44 ,  G11C29/76 ,  G11C29/785 ,  G11C2029/4402

Abstract: An integrated circuit device. The device includes an address input(s) configured to receive address information from an address stream from an address command bus coupled to a host controller and an address output(s) configured to drive address information, and is coupled to a plurality of memory (DRAM) devices provided on a DIMM. The device has an address match table comprising a non-volatile memory device configured to store at least a revised address corresponding to a spare memory location and a bad address of at least one of the plurality of memory (DRAM) devices. The device has a control module configured to process and determine whether each address matches with a stored address in the address match table to identify the bad address and configured to replace the bad address with the revised address of the spare memory location.

Abstract translation: 集成电路器件。 该设备包括被配置为从地址流接收地址信息的地址输入，该地址信息来自耦合到主机控制器的地址命令总线和被配置为驱动地址信息的地址输出，并被耦合到多个存储器 DRAM）设备。 该设备具有包括非易失性存储器设备的地址匹配表，其被配置为至少存储对应于多个存储器（DRAM）设备中的至少一个的备用存储器位置和不良地址的修改地址。 该设备具有控制模块，该控制模块被配置为处理并确定每个地址是否与地址匹配表中存储的地址相匹配，以识别不良地址并将其配置为用备用存储器位置的修改地址替换坏地址。

公开(公告)号：US08861277B1

公开(公告)日：2014-10-14

申请号：US13791814

申请日：2013-03-08

Applicant: Inphi Corporation

Inventor： Hamid Reza Rategh ,  David T. Wang ,  Lawrence Tse

IPC: G11C11/34 ,  G11C16/08 ,  G11C29/04 ,  G11C8/06

CPC classification number: G11C29/04 ,  G11C5/04 ,  G11C7/1012 ,  G11C8/06 ,  G11C11/413 ,  G11C16/08 ,  G11C29/08 ,  G11C29/44 ,  G11C29/76 ,  G11C29/785 ,  G11C2029/4402

Abstract: An integrated circuit device. The device includes an address input(s) configured to receive address information from an address stream from an address command bus coupled to a host controller and an address output(s) configured to drive address information, and is coupled to a plurality of memory (DRAM) devices provided on a DIMM. The device has an address match table comprising a non-volatile memory device configured to store at least a revised address corresponding to a spare memory location and a bad address of at least one of the plurality of memory (DRAM) devices. The device has a control module configured to process and determine whether each address matches with a stored address in the address match table to identify the bad address and configured to replace the bad address with the revised address of the spare memory location.

Abstract translation: 集成电路器件。 该设备包括被配置为从地址流接收地址信息的地址输入，该地址信息来自耦合到主机控制器的地址命令总线和被配置为驱动地址信息的地址输出，并被耦合到多个存储器 DRAM）设备。 该设备具有包括非易失性存储器设备的地址匹配表，其被配置为至少存储对应于多个存储器（DRAM）设备中的至少一个的备用存储器位置和不良地址的修改地址。 该设备具有控制模块，该控制模块被配置为处理并确定每个地址是否与地址匹配表中存储的地址相匹配，以识别不良地址并将其配置为用备用存储器位置的修改地址替换坏地址。