公开(公告)号：US10148357B1

公开(公告)日：2018-12-04

申请号：US15604196

申请日：2017-05-24

Applicant: INPHI CORPORATION

Inventor： Halil Cirit ,  Karthik Gopalakrishnan ,  Karim Abdelhalim ,  Jorge Pernillo ,  Lawrence Tse

IPC: H04B10/50 ,  H04B10/27

Abstract: Non-ideal downstream loading of a differential driver in a single ended circuit driving a communications laser—e.g., Electro absorption Modulated Laser (EML)—may be compensated by deploying a second matching network at the non-functional (terminated) driver output node. Certain embodiments may further compensate for distortion arising from circuit non-ideality, by introducing a laser replica downstream of the second matching network to mimic electrical properties of the laser. Embodiments may sufficiently compensate for downstream circuit non-ideality to allow replacing the bulky choke inductor of a bias tee, with a resistor. Substituting a resistor for a more complex inductor structure can simplify design and fabrication of the single-ended driver circuit, and also reduce footprint by eliminating area formerly occupied by the choke inductor. Embodiments may be particularly suited to bridge integration with other system components undergoing design migration toward double-ended modulator circuit architectures featuring a differential driver.

公开(公告)号：US10122472B2

公开(公告)日：2018-11-06

申请号：US15195863

申请日：2016-06-28

Applicant: INPHI CORPORATION

Inventor： Kevin Parker ,  Lawrence Tse ,  Kenji Suzuki ,  Brian Wall ,  Stephane Dallaire ,  Florin Pera

IPC: H04B10/66 ,  H04L25/03

Abstract: An optical receiver that recovers data is disclosed. The optical receiver includes a photodetector configured to convert an optical signal into a current signal, and a TIA (Transimpedance Amplifier) configured to operate according to a set of parameters to convert the current signal to a voltage signal. The optical receiver also includes an equalizer configured to process the voltage signal to produce a processed signal having recovered data from the optical signal, and to produce one or more equalization metrics. According to an embodiment of the disclosure, the optical receiver has a feedback processor configured to automatically tune operation of the TIA by adjusting at least one of the parameters of the TIA based on the one or more equalization metrics. This may effect a change in performance or power consumption of the optical receiver while receiving and recovering data. A corresponding method for recovering data is also disclosed.

公开(公告)号：US09240248B2

公开(公告)日：2016-01-19

申请号：US14473872

申请日：2014-08-29

Applicant: INPHI CORPORATION

Inventor： Hamid Reza Rategh ,  David T. Wang ,  Lawrence Tse

IPC: G11C11/34 ,  G11C29/04 ,  G11C8/06 ,  G11C5/04 ,  G11C29/44 ,  G11C7/10 ,  G11C11/413 ,  G11C16/08 ,  G11C29/00 ,  G11C29/08

CPC classification number: G11C29/04 ,  G11C5/04 ,  G11C7/1012 ,  G11C8/06 ,  G11C11/413 ,  G11C16/08 ,  G11C29/08 ,  G11C29/44 ,  G11C29/76 ,  G11C29/785 ,  G11C2029/4402

Abstract: An integrated circuit device. The device includes an address input(s) configured to receive address information from an address stream from an address command bus coupled to a host controller and an address output(s) configured to drive address information, and is coupled to a plurality of memory (DRAM) devices provided on a DIMM. The device has an address match table comprising a non-volatile memory device configured to store at least a revised address corresponding to a spare memory location and a bad address of at least one of the plurality of memory (DRAM) devices. The device has a control module configured to process and determine whether each address matches with a stored address in the address match table to identify the bad address and configured to replace the bad address with the revised address of the spare memory location.

Abstract translation: 集成电路器件。 该设备包括被配置为从地址流接收地址信息的地址输入，该地址信息来自耦合到主机控制器的地址命令总线和被配置为驱动地址信息的地址输出，并被耦合到多个存储器 DRAM）设备。 该设备具有包括非易失性存储器设备的地址匹配表，其被配置为至少存储对应于多个存储器（DRAM）设备中的至少一个的备用存储器位置和不良地址的修改地址。 该设备具有控制模块，该控制模块被配置为处理并确定每个地址是否与地址匹配表中存储的地址相匹配，以识别不良地址并将其配置为用备用存储器位置的修改地址替换坏地址。

公开(公告)号：US08996960B1

公开(公告)日：2015-03-31

申请号：US13797583

申请日：2013-03-12

Applicant: Inphi Corporation

Inventor： Nirmal Raj Saxena ,  David Wang ,  Hamid Rategh ,  Lawrence Tse

IPC: G11C29/00 ,  H03M13/17

CPC classification number: H03M13/17 ,  G06F11/1048

Abstract: Techniques for operating a DIMM apparatus. The apparatus comprises a plurality of DRAM devices numbered from 0 through N−1, where N is an integer greater than seven (7), each of the DRAM devices is configured in a substrate module; a buffer integrated circuit device comprising a plurality of data buffers (DB) numbered from 0 through N−1, where N is an integer greater than seven (7), each of the data buffers corresponds to one of the DRAM devices; and a plurality of error correcting modules (“ECMs”) associated with the plurality of DRAM devices.

Abstract translation: 操作DIMM装置的技术。 该装置包括从0到N-1编号的多个DRAM器件，其中N是大于7（7）的整数，每个DRAM器件被配置在衬底模块中; 包括从0到N-1编号的多个数据缓冲器（DB）的缓冲器集成电路器件，其中N是大于7（7）的整数，每个数据缓冲器对应于一个DRAM器件; 以及与多个DRAM设备相关联的多个纠错模块（“ECM”）。

公开(公告)号：US08861277B1

公开(公告)日：2014-10-14

申请号：US13791814

申请日：2013-03-08

Applicant: Inphi Corporation

Inventor： Hamid Reza Rategh ,  David T. Wang ,  Lawrence Tse

IPC: G11C11/34 ,  G11C16/08 ,  G11C29/04 ,  G11C8/06

CPC classification number: G11C29/04 ,  G11C5/04 ,  G11C7/1012 ,  G11C8/06 ,  G11C11/413 ,  G11C16/08 ,  G11C29/08 ,  G11C29/44 ,  G11C29/76 ,  G11C29/785 ,  G11C2029/4402

Abstract: An integrated circuit device. The device includes an address input(s) configured to receive address information from an address stream from an address command bus coupled to a host controller and an address output(s) configured to drive address information, and is coupled to a plurality of memory (DRAM) devices provided on a DIMM. The device has an address match table comprising a non-volatile memory device configured to store at least a revised address corresponding to a spare memory location and a bad address of at least one of the plurality of memory (DRAM) devices. The device has a control module configured to process and determine whether each address matches with a stored address in the address match table to identify the bad address and configured to replace the bad address with the revised address of the spare memory location.

Abstract translation: 集成电路器件。 该设备包括被配置为从地址流接收地址信息的地址输入，该地址信息来自耦合到主机控制器的地址命令总线和被配置为驱动地址信息的地址输出，并被耦合到多个存储器 DRAM）设备。 该设备具有包括非易失性存储器设备的地址匹配表，其被配置为至少存储对应于多个存储器（DRAM）设备中的至少一个的备用存储器位置和不良地址的修改地址。 该设备具有控制模块，该控制模块被配置为处理并确定每个地址是否与地址匹配表中存储的地址相匹配，以识别不良地址并将其配置为用备用存储器位置的修改地址替换坏地址。

公开(公告)号：US20170373761A1

公开(公告)日：2017-12-28

申请号：US15195863

申请日：2016-06-28

Applicant: INPHI CORPORATION

Inventor： Kevin Parker ,  Lawrence Tse ,  Kenji Suzuki ,  Brian Wall ,  Stephane Dallaire ,  Florin Pera

IPC: H04B10/66 ,  H04L25/03

CPC classification number: H04B10/66 ,  H04L25/03006

Abstract: An optical receiver that recovers data is disclosed. The optical receiver includes a photodetector configured to convert an optical signal into a current signal, and a TIA (Transimpedance Amplifier) configured to operate according to a set of parameters to convert the current signal to a voltage signal. The optical receiver also includes an equalizer configured to process the voltage signal to produce a processed signal having recovered data from the optical signal, and to produce one or more equalization metrics. According to an embodiment of the disclosure, the optical receiver has a feedback processor configured to automatically tune operation of the TIA by adjusting at least one of the parameters of the TIA based on the one or more equalization metrics. This may effect a change in performance or power consumption of the optical receiver while receiving and recovering data. A corresponding method for recovering data is also disclosed.