FORWARD ERROR CORRECTION (FEC) EMULATOR

    公开(公告)号:US20180123613A1

    公开(公告)日:2018-05-03

    申请号:US15337136

    申请日:2016-10-28

    CPC classification number: H03M13/015 H03M13/1515 H03M13/158

    Abstract: Embodiments relate to the emulation of the effect of Forward Error Correction (FEC) codes, e.g., GF10 Reed Solomon (RS) FEC codes, on the bit error ratio (BER) of received Pseudo-Random Binary Sequences (PRBS) patterns. In particular, embodiments group errors into RS-FEC symbols and codewords in order to determine if the errors are correctable. By emulating the error correction capabilities of FEC codes in order to determine which errors are correctable by the code, embodiments afford a more accurate representation of the post-FEC BER of RS FEC codes from links carrying PRBS patterns. This FEC code emulation provides error correction statistics, for stand-alone use or for error correction in connection with Bit Error Rate Testers (BERTs).

    MULTIPLEXERS WITH PROTECTION SWITCHING
    2.
    发明申请

    公开(公告)号:US20190132185A1

    公开(公告)日:2019-05-02

    申请号:US16232821

    申请日:2018-12-26

    Abstract: The present invention is directed to data communication. In certain embodiments, the present invention provides switching mechanism for choosing between redundant communication links. Data received from a first set of communication links are processed to have alignment markers removed, and first figure of merit value is determined based on the data without alignment markers. Similarly, a second figure of merit value is determined for the data received from the second set of communication links. A switch selects between the first set of communication links and the second set of communication links based on their respective figure of merit values. Alignment markers are inserted into the data transmitted through the selected set of data links. There are other embodiments as well.

    FORWARD ERROR CORRECTION (FEC) EMULATOR
    4.
    发明申请

    公开(公告)号:US20190165806A1

    公开(公告)日:2019-05-30

    申请号:US16262148

    申请日:2019-01-30

    Abstract: Embodiments relate to the emulation of the effect of Forward Error Correction (FEC) codes, e.g., GF10 Reed Solomon (RS) FEC codes, on the bit error ratio (BER) of received Pseudo-Random Binary Sequences (PRBS) patterns. In particular, embodiments group errors into RS-FEC symbols and codewords in order to determine if the errors are correctable. By emulating the error correction capabilities of FEC codes in order to determine which errors are correctable by the code, embodiments afford a more accurate representation of the post-FEC BER of RS FEC codes from links carrying PRBS patterns. This FEC code emulation provides error correction statistics, for stand-alone use or for error correction in connection with Bit Error Rate Testers (BERTs).

    MULTIPLEXERS WITH PROTECTION SWITCHING
    5.
    发明申请

    公开(公告)号:US20190052513A1

    公开(公告)日:2019-02-14

    申请号:US15987808

    申请日:2018-05-23

    Abstract: The present invention is directed to data communication. In certain embodiments, the present invention provides switching mechanism for choosing between redundant communication links. Data received from a first set of communication links are processed to have alignment markers removed, and first figure of merit value is determined based on the data without alignment markers. Similarly, a second figure of merit value is determined for the data received from the second set of communication links. A switch selects between the first set of communication links and the second set of communication links based on their respective figure of merit values. Alignment markers are inserted into the data transmitted through the selected set of data links. There are other embodiments as well.

    FORWARD ERROR CORRECTION (FEC) EMULATOR
    6.
    发明申请

    公开(公告)号:US20200228139A1

    公开(公告)日:2020-07-16

    申请号:US16828559

    申请日:2020-03-24

    Abstract: Embodiments relate to the emulation of the effect of Forward Error Correction (FEC) codes, e.g., GF10 Reed Solomon (RS) FEC codes, on the bit error ratio (BER) of received Pseudo-Random Binary Sequences (PRBS) patterns. In particular, embodiments group errors into RS-FEC symbols and codewords in order to determine if the errors are correctable. By emulating the error correction capabilities of FEC codes in order to determine which errors are correctable by the code, embodiments afford a more accurate representation of the post-FEC BER of RS FEC codes from links carrying PRBS patterns. This FEC code emulation provides error correction statistics, for stand-alone use or for error correction in connection with Bit Error Rate Testers (BERTs).

    FORWARD ERROR CORRECTION (FEC) EMULATOR
    8.
    发明申请

    公开(公告)号:US20180262209A1

    公开(公告)日:2018-09-13

    申请号:US15981844

    申请日:2018-05-16

    CPC classification number: H03M13/015 H03M13/1515 H03M13/158

    Abstract: Embodiments relate to the emulation of the effect of Forward Error Correction (FEC) codes, e.g., GF10 Reed Solomon (RS) FEC codes, on the bit error ratio (BER) of received Pseudo-Random Binary Sequences (PRBS) patterns. In particular, embodiments group errors into RS-FEC symbols and codewords in order to determine if the errors are correctable. By emulating the error correction capabilities of FEC codes in order to determine which errors are correctable by the code, embodiments afford a more accurate representation of the post-FEC BER of RS FEC codes from links carrying PRBS patterns. This FEC code emulation provides error correction statistics, for stand-alone use or for error correction in connection with Bit Error Rate Testers (BERTs).

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