公开(公告)号：US20210288672A1

公开(公告)日：2021-09-16

申请号：US16818864

申请日：2020-03-13

Applicant: INPHI CORPORATION

Inventor： Benjamin SMITH ,  Volodymyr SHVYDUN ,  Jamal RIANI ,  ILya LYUBOMIRSKY

IPC: H03M13/27 ,  H03M13/15

Abstract: The present invention is directed to data communication and encoding techniques. More specifically, an embodiment of the present invention provides a communication device that aligns a data stream with RS symbols. An interleaver interleaves RS symbols to generate an interleaved RS symbol data stream. Hamming parity blocks are generated for corresponding groups of RS symbols and inserted into the interleaved RS symbol data stream. There are other embodiments as well.

公开(公告)号：US20170026058A1

公开(公告)日：2017-01-26

申请号：US15283024

申请日：2016-09-30

Applicant: INPHI CORPORATION

Inventor： Volodymyr SHVYDUN

IPC: H03M13/00 ,  H04L1/00

CPC classification number: H03M13/617 ,  H03M13/1515 ,  H03M13/152 ,  H03M13/153 ,  H03M13/1545 ,  H03M13/159 ,  H04B10/60 ,  H04L1/0045

Abstract: The present invention is directed to data communication systems and methods thereof. According to various embodiments, the present invention provides a communication with a reconfigurable forward-error-correction (FEC) module. The FEC module processes data received from two or more communication lanes, and depending on the mode of operation, the FEC module can combine data from the two or more communication lanes and perform error correction on the combined data, or the FEC module can processes data from the two communications lanes separately and perform error correction independently for the each of the data communication lanes. There are other embodiments as well.

Abstract translation: 本发明涉及数据通信系统及其方法。 根据各种实施例，本发明提供与可重新配置的前向纠错（FEC）模块的通信。 FEC模块处理从两个或多个通信线路接收到的数据，并且根据操作模式，FEC模块可以组合来自两个或更多个通信线路的数据，并对组合的数据进行纠错，或者FEC模块可以处理数据 分别从两个通信通道执行针对每个数据通信车道的独立执行纠错。 还有其它实施例。

公开(公告)号：US20200228146A1

公开(公告)日：2020-07-16

申请号：US16831626

申请日：2020-03-26

Applicant: INPHI CORPORATION

Inventor： Volodymyr SHVYDUN

IPC: H03M13/00 ,  H04B10/60 ,  H04L1/00 ,  H03M13/15

Abstract: The present invention is directed to data communication systems and methods thereof. According to various embodiments, the present invention provides a communication with a reconfigurable forward-error-correction (FEC) module. The FEC module processes data received from two or more communication lanes, and depending on the mode of operation, the FEC module can combine data from the two or more communication lanes and perform error correction on the combined data, or the FEC module can processes data from the two communications lanes separately and perform error correction independently for the each of the data communication lanes. There are other embodiments as well.

公开(公告)号：US20190268091A1

公开(公告)日：2019-08-29

申请号：US16403408

申请日：2019-05-03

Applicant: INPHI CORPORATION

Inventor： Jamal RIANI ,  Benjamin P. SMITH ,  Volodymyr SHVYDUN ,  Sudeep BHOJA ,  Arash FARHOODFAR

IPC: H04L1/00 ,  H03M13/29 ,  H04B14/02

Abstract: The present invention is directed to data communication systems and techniques thereof. More specifically, embodiments of the present invention provide an FEC encoder that generates parity symbols that are embedded into FEC blocks. An FEC decoder determines whether to perform error correction based on the parity symbols. When performing error correction, the decoder selects a worst symbol from a segment of symbols, and the worst symbol is corrected. There are other embodiments as well.

公开(公告)号：US20220070556A1

公开(公告)日：2022-03-03

申请号：US17011941

申请日：2020-09-03

Applicant: INPHI CORPORATION

Inventor： Whay Sing LEE ,  Arash FARHOODFAR ,  Volodymyr SHVYDUN ,  Michael DUCKERING

IPC: H04Q11/00 ,  H04L1/00 ,  H04J14/02

Abstract: The present invention is direct to data communication. In a specific embodiment, multiple independent data streams, which are at a first data rate, are transcoded by separate communication pipelines into data blocks. The data blocks, associated with these separate and independent data streams, are multiplexed with alignment markers to generate an output data stream. The output data stream is transmitted at a second data rate, which is higher than the first data rate.

公开(公告)号：US20200343999A1

公开(公告)日：2020-10-29

申请号：US16928821

申请日：2020-07-14

Applicant: INPHI CORPORATION

Inventor： Jamal RIANI ,  Benjamin SMITH ,  Volodymyr SHVYDUN ,  Sudeep BHOJA ,  Arash FARHOODFAR

IPC: H04L1/00 ,  H04B14/02 ,  H03M13/29

Abstract: The present invention is directed to data communication systems and techniques thereof. More specifically, embodiments of the present invention provide an FEC encoder that generates parity symbols that are embedded into FEC blocks. An FEC decoder determines whether to perform error correction based on the parity symbols. When performing error correction, the decoder selects a worst symbol from a segment of symbols, and the worst symbol is corrected. There are other embodiments as well.

公开(公告)号：US20200220659A1

公开(公告)日：2020-07-09

申请号：US16824261

申请日：2020-03-19

Applicant: INPHI CORPORATION

Inventor： Jamal RIANI ,  Benjamin SMITH ,  Volodymyr SHVYDUN ,  Srinivas SWAMINATHAN ,  Arash Farhoodfar

IPC: H04L1/00

Abstract: The present invention is directed to data communication systems and techniques thereof. More specifically, embodiments of the present invention provide an FEC encoder that processes an interleaved data stream and generates parity symbols that are embedded into FEC blocks. An FEC decoder determines whether to perform error correction based on the parity symbols. When performing error correction, the decoder selects a worst symbol from a segment of symbols, and the worst symbol is corrected. There are other embodiments as well.

公开(公告)号：US20190089385A1

公开(公告)日：2019-03-21

申请号：US16192659

申请日：2018-11-15

Applicant: INPHI CORPORATION

Inventor： Volodymyr SHVYDUN

IPC: H03M13/00 ,  H03M13/15 ,  H04L1/00 ,  H04B10/60

Abstract: The present invention is directed to data communication systems and methods thereof. According to various embodiments, the present invention provides a communication with a reconfigurable forward-error-correction (FEC) module. The FEC module processes data received from two or more communication lanes, and depending on the mode of operation, the FEC module can combine data from the two or more communication lanes and perform error correction on the combined data, or the FEC module can processes data from the two communications lanes separately and perform error correction independently for the each of the data communication lanes. There are other embodiments as well.