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公开(公告)号:US20200014407A1
公开(公告)日:2020-01-09
申请号:US16575236
申请日:2019-09-18
Applicant: INPHI CORPORATION
Inventor: Benjamin SMITH , Arash FARHOODFAR , Stewart CROZIER , Frank R. KSCHISCHANG , Andrew HUNT
Abstract: For some applications such as high-speed communication over short-reach links, the complexity and associated high latency provided by existing modulators may be unsuitable. According to an aspect, the present disclosure provides a modulator that can reduce latency for applications such as 40G/100G communication over copper cables or SMF. The modulator has a symbol mapper for mapping a bit stream into symbols, and a multi-level encoder including an inner encoder and an outer encoder for encoding only a portion of the bit stream. In some implementations, the multi-level encoder is configured such that an information block size of the inner encoder is small and matches a field size of the outer encoder. Therefore, components that would be used to accommodate larger block sizes can be omitted. The effect is that complexity and latency can be reduced. According to another aspect, the present disclosure provides a demodulator that is complementary to the modulator.
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公开(公告)号:US20210288672A1
公开(公告)日:2021-09-16
申请号:US16818864
申请日:2020-03-13
Applicant: INPHI CORPORATION
Inventor: Benjamin SMITH , Volodymyr SHVYDUN , Jamal RIANI , ILya LYUBOMIRSKY
Abstract: The present invention is directed to data communication and encoding techniques. More specifically, an embodiment of the present invention provides a communication device that aligns a data stream with RS symbols. An interleaver interleaves RS symbols to generate an interleaved RS symbol data stream. Hamming parity blocks are generated for corresponding groups of RS symbols and inserted into the interleaved RS symbol data stream. There are other embodiments as well.
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公开(公告)号:US20180302108A1
公开(公告)日:2018-10-18
申请号:US16011483
申请日:2018-06-18
Applicant: INPHI CORPORATION
Inventor: Benjamin SMITH , Arash FARHOODFAR , Stewart CROZIER , Frank R. KSCHISCHANG , Andrew HUNT
CPC classification number: H03M13/2906 , H03M13/1515 , H04L1/0041 , H04L1/0042 , H04L1/0045 , H04L1/0057 , H04L1/006 , H04L1/0063 , H04L1/0065 , H04L25/4917 , H04L27/04
Abstract: For some applications such as high-speed communication over short-reach links, the complexity and associated high latency provided by existing modulators may be unsuitable. According to an aspect, the present disclosure provides a modulator that can reduce latency for applications such as 40G/100G communication over copper cables or SMF. The modulator has a symbol mapper for mapping a bit stream into symbols, and a multi-level encoder including an inner encoder and an outer encoder for encoding only a portion of the bit stream. In some implementations, the multi-level encoder is configured such that an information block size of the inner encoder is small and matches a field size of the outer encoder. Therefore, components that would be used to accommodate larger block sizes can be omitted. The effect is that complexity and latency can be reduced. According to another aspect, the present disclosure provides a demodulator that is complementary to the modulator.
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公开(公告)号:US20200343999A1
公开(公告)日:2020-10-29
申请号:US16928821
申请日:2020-07-14
Applicant: INPHI CORPORATION
Inventor: Jamal RIANI , Benjamin SMITH , Volodymyr SHVYDUN , Sudeep BHOJA , Arash FARHOODFAR
Abstract: The present invention is directed to data communication systems and techniques thereof. More specifically, embodiments of the present invention provide an FEC encoder that generates parity symbols that are embedded into FEC blocks. An FEC decoder determines whether to perform error correction based on the parity symbols. When performing error correction, the decoder selects a worst symbol from a segment of symbols, and the worst symbol is corrected. There are other embodiments as well.
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公开(公告)号:US20200220659A1
公开(公告)日:2020-07-09
申请号:US16824261
申请日:2020-03-19
Applicant: INPHI CORPORATION
Inventor: Jamal RIANI , Benjamin SMITH , Volodymyr SHVYDUN , Srinivas SWAMINATHAN , Arash Farhoodfar
IPC: H04L1/00
Abstract: The present invention is directed to data communication systems and techniques thereof. More specifically, embodiments of the present invention provide an FEC encoder that processes an interleaved data stream and generates parity symbols that are embedded into FEC blocks. An FEC decoder determines whether to perform error correction based on the parity symbols. When performing error correction, the decoder selects a worst symbol from a segment of symbols, and the worst symbol is corrected. There are other embodiments as well.
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公开(公告)号:US20190068322A1
公开(公告)日:2019-02-28
申请号:US15693294
申请日:2017-08-31
Applicant: Inphi Corporation
Inventor: Benjamin SMITH , Jamal RIANI , Arash FARHOODFAR , Sudeep BHOJA
CPC classification number: H04L1/0057 , H03M13/19 , H03M13/251 , H03M13/2906 , H04L1/0041 , H04L1/0058 , H04L1/0059 , H04L1/0064 , H04L1/0071 , H04L1/0643 , H04L27/2627
Abstract: The present invention relates to data communication systems and methods thereof. More specifically, embodiments of the present invention provide a data transmission method. Data are encoded with staircase encoder, and staircase coded blocks are first interleaved then combined into outer code frames. Code frames additionally include sync words and padding bits. A second interleaving is applied to the bits of the code frames, and Hamming encoding is performed on the output of the second interleaver. Hamming codewords are Gray-mapped to dual-polarized quadrature-amplitude-modulation (DP-QAM) symbols, and a third interleaving of the symbols from a set of successive Hamming codewords is performed. Pilot symbols are inserted periodically into the stream of DP-QAM symbols. There are other embodiments as well.
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