公开(公告)号：US20210143100A1

公开(公告)日：2021-05-13

申请号：US16681164

申请日：2019-11-12

Applicant: Intel Corporation

Inventor： Nanda Kumar Chakravarthi ,  Kwame Nkrumah Eason ,  Abhinav Tripathi ,  Ebony Lynn Mays ,  Jessica Sevanne Kachian ,  Ralf Buengener

IPC: H01L23/535 ,  H01L27/11556 ,  H01L27/11582 ,  H01L23/522 ,  H01L23/528 ,  H01L21/768

Abstract: A memory array including integrated word line (WL) contact structures are disclosed. The memory array comprises a plurality of WLs that includes at least a first WL and a second WL. An integrated WL contact structure includes a first WL contact and a second WL contact for the first WL and the second WL, respectively. The second WL contact extends through the first WL contact. For example, the second WL contact is nested within the first WL contact. An intervening isolation material isolates the second WL contact from the first WL contact. In an example, the second WL contact extends through a hole in the first WL to reach the second WL. The isolation material isolates the second WL contact from sidewalls of the hole in the first WL.

公开(公告)号：US12167592B2

公开(公告)日：2024-12-10

申请号：US17442582

申请日：2019-06-10

Applicant: INTEL CORPORATION

Inventor： Nanda Kumar Chakravarthi ,  David Meyaard ,  Abhinav Tripathi ,  Liu Liu

IPC: H01L27/11524 ,  H10B41/20 ,  H10B41/35 ,  H10B43/20 ,  H10B43/35

Abstract: Embodiments of the present disclosure are directed towards a memory device including a top wordline contact located in a region that is protected from erosion during a planarization process, e.g., chemical mechanical polish (CMP). In embodiments, a plurality of wordlines are formed in a stack of multiple layers and a plurality of wordline contacts are formed to intersect with the plurality of wordlines. In embodiments, the stack forms a staircase and each of the plurality of wordline contacts lands on a corresponding each of the wordlines proximate to an edge of the staircase such that a top wordline contact lands in a region on a top wordline previously covered by a sacrificial layer. In some embodiments, the region is proximate to a raised notch at an edge of the staircase. Other embodiments may be described and claimed.

公开(公告)号：US20230402389A1

公开(公告)日：2023-12-14

申请号：US18235766

申请日：2023-08-18

Applicant: Intel Corporation

Inventor： Nanda Kumar Chakravarthi ,  Kwame Nkrumah Eason ,  Abhinav Tripathi ,  Ebony Lynn MAYS ,  Jessica Sevanne Kachian ,  Ralf Buengener

IPC: H01L23/535 ,  H01L21/768 ,  H01L23/528 ,  H01L23/522 ,  H10B41/27 ,  H10B43/27

CPC classification number: H01L23/535 ,  H01L21/76895 ,  H01L23/5283 ,  H01L21/76805 ,  H01L23/5226 ,  H10B41/27 ,  H10B43/27

Abstract: A memory array including integrated word line (WL) contact structures are disclosed. The memory array comprises a plurality of WLs that includes at least a first WL and a second WL. An integrated WL contact structure includes a first WL contact and a second WL contact for the first WL and the second WL, respectively. The second WL contact extends through the first WL contact. For example, the second WL contact is nested within the first WL contact. An intervening isolation material isolates the second WL contact from the first WL contact. In an example, the second WL contact extends through a hole in the first WL to reach the second WL. The isolation material isolates the second WL contact from sidewalls of the hole in the first WL.