公开(公告)号：US11216719B2

公开(公告)日：2022-01-04

申请号：US16009456

申请日：2018-06-15

Applicant: INTEL CORPORATION

Inventor： Somdeb Majumdar ,  Ron Banner ,  Marcel Nassar ,  Lior Storfer ,  Adnan Agbaria ,  Evren Tumer ,  Tristan Webb ,  Xin Wang

IPC: G06N3/04 ,  G06N3/08 ,  G06N3/063

Abstract: Logic may quantize a primary neural network. Logic may generate, by a secondary neural network logic circuitry for a primary neural network logic circuitry, quantization parameters. The primary neural network logic circuitry may comprise a primary neural network with multiple layers trainable with an objective function. Each of the multiple layers of the primary neural network may comprise multiple tensors. The secondary neural network logic circuitry may comprise one or more secondary neural networks trainable with the objective function to output the quantization parameters to the tensors.

公开(公告)号：US10817567B2

公开(公告)日：2020-10-27

申请号：US15941168

申请日：2018-03-30

Applicant: INTEL CORPORATION

Inventor： Ehud Cohen ,  Adnan Agbaria

IPC: G06F16/00 ,  G06F16/901 ,  G06N5/02 ,  G06F16/9038 ,  G06N20/00

Abstract: Techniques and apparatus for providing graph compression structures for graph information are described. In one embodiment, for example, an apparatus may include at least one memory, at least one processing circuitry, and logic, coupled to the at least one processing circuitry, to access graph information comprising a plurality of nodes, define a unique index for each of the plurality of nodes, determine whether each of the plurality of nodes has at least one neighbor node, and generate a graph compression structure comprising an entry for each of the plurality of nodes having at least one neighbor node and an adjacency list comprising an array of neighbor nodes of each entry.

公开(公告)号：US20190042662A1

公开(公告)日：2019-02-07

申请号：US15941168

申请日：2018-03-30

Applicant: INTEL CORPORATION

Inventor： Ehud Cohen ,  Adnan Agbaria

IPC: G06F17/30 ,  G06N5/02

Abstract: Techniques and apparatus for providing graph compression structures for graph information are described. In one embodiment, for example, an apparatus may include at least one memory, at least one processing circuitry, and logic, coupled to the at least one processing circuitry, to access graph information comprising a plurality of nodes, define a unique index for each of the plurality of nodes, determine whether each of the plurality of nodes has at least one neighbor node, and generate a graph compression structure comprising an entry for each of the plurality of nodes having at least one neighbor node and an adjacency list comprising an array of neighbor nodes of each entry.