公开(公告)号：US10268579B2

公开(公告)日：2019-04-23

申请号：US15477055

申请日：2017-04-01

Applicant: Intel Corporation

Inventor： Sanjeev Kumar ,  Christopher J. Hughes ,  Partha Kundu ,  Anthony Nguyen

IPC: G06F12/084 ,  G06F12/0846 ,  G06F12/0806 ,  G06F9/52 ,  G06F12/0831 ,  G06F9/30 ,  G06F9/38 ,  G06F9/46

Abstract: Embodiments of the invention relate a hybrid hardware and software implementation of transactional memory accesses in a computer system. A processor including a transactional cache and a regular cache is utilized in a computer system that includes a policy manager to select one of a first mode (a hardware mode) or a second mode (a software mode) to implement transactional memory accesses. In the hardware mode the transactional cache is utilized to perform read and write memory operations and in the software mode the regular cache is utilized to perform read and write memory operations.

公开(公告)号：US20190026158A1

公开(公告)日：2019-01-24

申请号：US15872762

申请日：2018-01-16

Applicant: Intel Corporation

Inventor： Anthony Nguyen ,  Engin Ipek ,  Victor Lee ,  Daehyun Kim ,  Mikhail Smelyanskiy

IPC: G06F9/50 ,  G06F15/80

Abstract: Methods and apparatus to provide virtualized vector processing are described. In one embodiment, one or more operations corresponding to a virtual vector request are distributed to one or more processor cores for execution.

公开(公告)号：US10102123B2

公开(公告)日：2018-10-16

申请号：US15299452

申请日：2016-10-20

Applicant: INTEL CORPORATION

Inventor： Sanjeev Kumar ,  Christopher J. Hughes ,  Partha Kundu ,  Anthony Nguyen

IPC: G06F12/08 ,  G06F12/0806 ,  G06F9/52 ,  G06F12/0831 ,  G06F12/0846 ,  G06F9/30 ,  G06F9/38 ,  G06F9/46 ,  G06F12/084

Abstract: Embodiments of the invention relate a hybrid hardware and software implementation of transactional memory accesses in a computer system. A processor including a transactional cache and a regular cache is utilized in a computer system that includes a policy manager to select one of a first mode (a hardware mode) or a second mode (a software mode) to implement transactional memory accesses. In the hardware mode the transactional cache is utilized to perform read and write memory operations and in the software mode the regular cache is utilized to perform read and write memory operations.

公开(公告)号：US10768989B2

公开(公告)日：2020-09-08

申请号：US15872762

申请日：2018-01-16

Applicant: Intel Corporation

Inventor： Anthony Nguyen ,  Engin Ipek ,  Victor Lee ,  Daehyun Kim ,  Mikhail Smelyanskiy

IPC: G06F9/50 ,  G06F15/80

Abstract: Methods and apparatus to provide virtualized vector processing are described. In one embodiment, one or more operations corresponding to a virtual vector request are distributed to one or more processor cores for execution.

公开(公告)号：US10180903B2

公开(公告)日：2019-01-15

申请号：US15477052

申请日：2017-04-01

Applicant: Intel Corporation

Inventor： Sanjeev Kumar ,  Christopher J. Hughes ,  Partha Kundu ,  Anthony Nguyen

IPC: G06F12/0846 ,  G06F12/0806 ,  G06F9/52 ,  G06F12/0831 ,  G06F9/30 ,  G06F9/38 ,  G06F9/46 ,  G06F12/084

Abstract: Embodiments of the invention relate a hybrid hardware and software implementation of transactional memory accesses in a computer system. A processor including a transactional cache and a regular cache is utilized in a computer system that includes a policy manager to select one of a first mode (a hardware mode) or a second mode (a software mode) to implement transactional memory accesses. In the hardware mode the transactional cache is utilized to perform read and write memory operations and in the software mode the regular cache is utilized to perform read and write memory operations.

公开(公告)号：US09529715B2

公开(公告)日：2016-12-27

申请号：US13843890

申请日：2013-03-15

Applicant: Intel Corporation

Inventor： Sanjeev Kumar ,  Christopher J. Hughes ,  Partha Kundu ,  Anthony Nguyen

IPC: G06F12/08 ,  G06F9/46 ,  G06F9/52 ,  G06F9/30 ,  G06F9/38

CPC classification number: G06F12/0806 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30087 ,  G06F9/30145 ,  G06F9/3834 ,  G06F9/3857 ,  G06F9/3859 ,  G06F9/467 ,  G06F9/528 ,  G06F12/0831 ,  G06F12/084 ,  G06F12/0848 ,  G06F2212/60 ,  G06F2212/621

Abstract: Embodiments of the invention relate a hybrid hardware and software implementation of transactional memory accesses in a computer system. A processor including a transactional cache and a regular cache is utilized in a computer system that includes a policy manager to select one of a first mode (a hardware mode) or a second mode (a software mode) to implement transactional memory accesses. In the hardware mode the transactional cache is utilized to perform read and write memory operations and in the software mode the regular cache is utilized to perform read and write memory operations.