公开(公告)号：US08954674B2

公开(公告)日：2015-02-10

申请号：US14048291

申请日：2013-10-08

Applicant: Intel Corporation

Inventor： Daehyun Kim ,  Christopher J. Hughes ,  Yen-Kuang Chen ,  Partha Kundu

IPC: G06F12/00 ,  G11C7/10 ,  G06F12/08

CPC classification number: G06F12/0806 ,  G06F12/08 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0817 ,  G06F12/0862 ,  G06F12/0877 ,  G06F12/0891 ,  G06F12/0897 ,  G06F2212/6026 ,  G06F2212/62 ,  G11C7/1072 ,  G11C7/1075 ,  Y02D10/13

Abstract: A scatter/gather technique optimizes unstructured streaming memory accesses, providing off-chip bandwidth efficiency by accessing only useful data at a fine granularity, and off-loading memory access overhead by supporting address calculation, data shuffling, and format conversion.

Abstract translation: 分散/收集技术优化非结构化流式存储器访问，通过仅访问精细粒度的有用数据来提供片外带宽效率，并通过支持地址计算，数据混洗和格式转换来卸载内存访问开销。

公开(公告)号：US10585667B2

公开(公告)日：2020-03-10

申请号：US15900030

申请日：2018-02-20

Applicant: Intel Corporation

Inventor： Edward Grochowski ,  Hong Wang ,  John P. Shen ,  Perry H. Wang ,  Jamison D. Collins ,  James Held ,  Partha Kundu ,  Raya Leviathan ,  Tin-Fook Ngai

IPC: G06F9/30 ,  G06F9/38

Abstract: A method and system to provide user-level multithreading are disclosed. The method according to the present techniques comprises receiving programming instructions to execute one or more shared resource threads (shreds) via an instruction set architecture (ISA). One or more instruction pointers are configured via the ISA; and the one or more shreds are executed simultaneously with a microprocessor, wherein the microprocessor includes multiple instruction sequencers.

公开(公告)号：US10268579B2

公开(公告)日：2019-04-23

申请号：US15477055

申请日：2017-04-01

Applicant: Intel Corporation

Inventor： Sanjeev Kumar ,  Christopher J. Hughes ,  Partha Kundu ,  Anthony Nguyen

IPC: G06F12/084 ,  G06F12/0846 ,  G06F12/0806 ,  G06F9/52 ,  G06F12/0831 ,  G06F9/30 ,  G06F9/38 ,  G06F9/46

Abstract: Embodiments of the invention relate a hybrid hardware and software implementation of transactional memory accesses in a computer system. A processor including a transactional cache and a regular cache is utilized in a computer system that includes a policy manager to select one of a first mode (a hardware mode) or a second mode (a software mode) to implement transactional memory accesses. In the hardware mode the transactional cache is utilized to perform read and write memory operations and in the software mode the regular cache is utilized to perform read and write memory operations.

公开(公告)号：US10102123B2

公开(公告)日：2018-10-16

申请号：US15299452

申请日：2016-10-20

Applicant: INTEL CORPORATION

Inventor： Sanjeev Kumar ,  Christopher J. Hughes ,  Partha Kundu ,  Anthony Nguyen

IPC: G06F12/08 ,  G06F12/0806 ,  G06F9/52 ,  G06F12/0831 ,  G06F12/0846 ,  G06F9/30 ,  G06F9/38 ,  G06F9/46 ,  G06F12/084

Abstract: Embodiments of the invention relate a hybrid hardware and software implementation of transactional memory accesses in a computer system. A processor including a transactional cache and a regular cache is utilized in a computer system that includes a policy manager to select one of a first mode (a hardware mode) or a second mode (a software mode) to implement transactional memory accesses. In the hardware mode the transactional cache is utilized to perform read and write memory operations and in the software mode the regular cache is utilized to perform read and write memory operations.

公开(公告)号：US08966180B2

公开(公告)日：2015-02-24

申请号：US13782515

申请日：2013-03-01

Applicant: Intel Corporation

Inventor： Daehyun Kim ,  Christopher J. Hughes ,  Yen-Kuang Chen ,  Partha Kundu

IPC: G06F12/00 ,  G11C7/10 ,  G06F12/08

CPC classification number: G06F12/0806 ,  G06F12/08 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0817 ,  G06F12/0862 ,  G06F12/0877 ,  G06F12/0891 ,  G06F12/0897 ,  G06F2212/6026 ,  G06F2212/62 ,  G11C7/1072 ,  G11C7/1075 ,  Y02D10/13

Abstract: A scatter/gather technique optimizes unstructured streaming memory accesses, providing off-chip bandwidth efficiency by accessing only useful data at a fine granularity, and off-loading memory access overhead by supporting address calculation, data shuffling, and format conversion.

公开(公告)号：US09323672B2

公开(公告)日：2016-04-26

申请号：US14585573

申请日：2014-12-30

Applicant: Intel Corporation

Inventor： Daehyun Kim ,  Christopher J. Hughes ,  Yen-Kuang Chen ,  Partha Kundu

IPC: G06F12/08 ,  G11C7/10

CPC classification number: G06F12/0806 ,  G06F12/08 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0817 ,  G06F12/0862 ,  G06F12/0877 ,  G06F12/0891 ,  G06F12/0897 ,  G06F2212/6026 ,  G06F2212/62 ,  G11C7/1072 ,  G11C7/1075 ,  Y02D10/13

Abstract: A scatter/gather technique optimizes unstructured streaming memory accesses, providing off-chip bandwidth efficiency by accessing only useful data at a fine granularity, and off-loading memory access overhead by supporting address calculation, data shuffling, and format conversion.

公开(公告)号：US09952859B2

公开(公告)日：2018-04-24

申请号：US15088043

申请日：2016-03-31

Applicant: Intel Corporation

Inventor： Ed Grochowski ,  Hong Wang ,  John P. Shen ,  Perry H. Wang ,  Jamison D. Collins ,  James Held ,  Partha Kundu ,  Raya Leviathan ,  Tin-Fook Ngai

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30003 ,  G06F9/30087 ,  G06F9/3009 ,  G06F9/30101 ,  G06F9/3013 ,  G06F9/384 ,  G06F9/3851

Abstract: A method and system to provide user-level multithreading are disclosed. The method according to the present techniques comprises receiving programming instructions to execute one or more shared resource threads (shreds) via an instruction set architecture (ISA). One or more instruction pointers are configured via the ISA; and the one or more shreds are executed simultaneously with a microprocessor, wherein the microprocessor includes multiple instruction sequencers.

公开(公告)号：US20160216971A1

公开(公告)日：2016-07-28

申请号：US15088043

申请日：2016-03-31

Applicant: Intel Corporation

Inventor： Ed Grochowski ,  Hong Wang ,  John P. Shen ,  Perry H. Wang ,  Jamison D. Collins ,  James Held ,  Partha Kundu ,  Raya Leviathan ,  Tin-Fook Ngai

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/30003 ,  G06F9/30087 ,  G06F9/3009 ,  G06F9/30101 ,  G06F9/3013 ,  G06F9/384 ,  G06F9/3851

Abstract: A method and system to provide user-level multithreading are disclosed. The method according to the present techniques comprises receiving programming instructions to execute one or more shared resource threads (shreds) via an instruction set architecture (ISA). One or more instruction pointers are configured via the ISA; and the one or more shreds are executed simultaneously with a microprocessor, wherein the microprocessor includes multiple instruction sequencers.

公开(公告)号：US20150178200A1

公开(公告)日：2015-06-25

申请号：US14585573

申请日：2014-12-30

Applicant: Intel Corporation

Inventor： Daehyun Kim ,  Christopher J. Hughes ,  Yen-Kuang Chen ,  Partha Kundu

IPC: G06F12/08

CPC classification number: G06F12/0806 ,  G06F12/08 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0817 ,  G06F12/0862 ,  G06F12/0877 ,  G06F12/0891 ,  G06F12/0897 ,  G06F2212/6026 ,  G06F2212/62 ,  G11C7/1072 ,  G11C7/1075 ,  Y02D10/13

Abstract: A scatter/gather technique optimizes unstructured streaming memory accesses, providing off-chip bandwidth efficiency by accessing only useful data at a fine granularity, and off-loading memory access overhead by supporting address calculation, data shuffling, and format conversion.

Abstract translation: 分散/收集技术优化非结构化流式存储器访问，通过仅访问精细粒度的有用数据来提供片外带宽效率，并通过支持地址计算，数据混洗和格式转换来卸载内存访问开销。

公开(公告)号：US10180903B2

公开(公告)日：2019-01-15

申请号：US15477052

申请日：2017-04-01

Applicant: Intel Corporation

Inventor： Sanjeev Kumar ,  Christopher J. Hughes ,  Partha Kundu ,  Anthony Nguyen

IPC: G06F12/0846 ,  G06F12/0806 ,  G06F9/52 ,  G06F12/0831 ,  G06F9/30 ,  G06F9/38 ,  G06F9/46 ,  G06F12/084

Abstract: Embodiments of the invention relate a hybrid hardware and software implementation of transactional memory accesses in a computer system. A processor including a transactional cache and a regular cache is utilized in a computer system that includes a policy manager to select one of a first mode (a hardware mode) or a second mode (a software mode) to implement transactional memory accesses. In the hardware mode the transactional cache is utilized to perform read and write memory operations and in the software mode the regular cache is utilized to perform read and write memory operations.