公开(公告)号：US20200327256A1

公开(公告)日：2020-10-15

申请号：US16912076

申请日：2020-06-25

Applicant: INTEL CORPORATION

Inventor： JOSHUA FENDER ,  UTKARSH Y. KAKAIYA ,  MOHAN NAIR ,  BRIAN MORRIS ,  PRATIK MAROLIA

IPC: G06F21/76 ,  H04L29/08 ,  G06F11/14 ,  G06F1/3206 ,  G06F21/54 ,  G06F1/324 ,  G06F21/74 ,  H04L29/06 ,  G06F1/20 ,  G06F1/3287

Abstract: Various embodiments are generally directed to securing systems that include hardware accelerators, such as FPGA-based accelerators, and privileged system components. Some embodiments may provide a security broker. In various embodiments, the security broker may provide interfaces between the hardware accelerator and the privileged component. Some embodiments may receive an instruction from the hardware accelerator targeting the privileged component, and validate the instruction based on a configuration. In some embodiments, upon determining the instruction is not validated, the instruction is restricted from further processing.