公开(公告)号：US20230161615A1

公开(公告)日：2023-05-25

申请号：US18153177

申请日：2023-01-11

Applicant: Intel Corporation

Inventor： SANJAY KUMAR ,  PHILIP R. LANTZ ,  KUN TIAN ,  UTKARSH Y. KAKAIYA ,  RAJESH M. SANKARAN

IPC: G06F9/455 ,  G06F9/30 ,  G06F12/1009

CPC classification number: G06F9/45558 ,  G06F9/30101 ,  G06F12/1009 ,  G06F2009/45579

Abstract: Techniques for transferring virtual machines and resource management in a virtualized computing environment are described. In one embodiment, for example, an apparatus may include at least one memory, at least one processor, and logic for transferring a virtual machine (VM), at least a portion of the logic comprised in hardware coupled to the at least one memory and the at least one processor, the logic to generate a plurality of virtualized capability registers for a virtual device (VDEV) by virtualizing a plurality of device-specific capability registers of a physical device to be virtualized by the VM, the plurality of virtualized capability registers comprising a plurality of device-specific capabilities of the physical device, determine a version of the physical device to support via a virtual machine monitor (VMM), and expose a subset of the virtualized capability registers associated with the version to the VM. Other embodiments are described and claimed.

公开(公告)号：US20230023329A1

公开(公告)日：2023-01-26

申请号：US17891180

申请日：2022-08-19

Applicant: Intel Corporation

Inventor： UTKARSH Y. KAKAIYA ,  RAJESH SANKARAN ,  GILBERT NEIGER ,  PHILIP LANTZ ,  SANJAY K. KUMAR

IPC: G06F9/34 ,  G06F9/30 ,  G06F12/109

Abstract: In one embodiment, a processor comprises: a first configuration register to store a pointer to a process address space identifier (PASID) table; and an execution circuit coupled to the first configuration register. The execution circuit, in response to a first instruction, is to obtain command data from a first location identified in a source operand of the first instruction, obtain a PASID table handle from the command data, access a first entry of the PASID table using the pointer from the first configuration register and the PASID table handle to obtain a PASID value, insert the PASID value into the command data, and send the command data to a device coupled to the processor. Other embodiments are described and claimed.

公开(公告)号：US20200319913A1

公开(公告)日：2020-10-08

申请号：US16909068

申请日：2020-06-23

Applicant: Intel Corporation

Inventor： SANJAY K. KUMAR ,  RAJESH SANKARAN ,  UTKARSH Y. KAKAIYA ,  PRATIK M. MAROLIA

IPC: G06F9/455 ,  G06F12/10

Abstract: In one embodiment, an apparatus includes an input/output virtualization (IOV) device comprising: at least one function circuit to be shared by a plurality of virtual machines (VMs); and a plurality of assignable device interfaces (ADIs) coupled to the at least one function circuit, wherein each of the plurality of ADIs is to be associated with one of the plurality of VMs and comprises a first process address space identifier (PASID) field to store a first PASID to identify a descriptor queue stored in a host address space and a second PASID field to store a second PASID to identify a data buffer located in a VM address space. Other embodiments are described and claimed.

公开(公告)号：US20240345841A1

公开(公告)日：2024-10-17

申请号：US18751604

申请日：2024-06-24

Applicant: Intel Corporation

Inventor： UTKARSH Y. KAKAIYA ,  RAJESH SANKARAN ,  GILBERT NEIGER ,  PHILIP LANTZ ,  SANJAY K. KUMAR

IPC: G06F9/34 ,  G06F9/30 ,  G06F12/109

CPC classification number: G06F9/34 ,  G06F9/30098 ,  G06F12/109 ,  G06F2212/657

Abstract: In one embodiment, a processor comprises: a first configuration register to store a pointer to a process address space identifier (PASID) table; and an execution circuit coupled to the first configuration register. The execution circuit, in response to a first instruction, is to obtain command data from a first location identified in a source operand of the first instruction, obtain a PASID table handle from the command data, access a first entry of the PASID table using the pointer from the first configuration register and the PASID table handle to obtain a PASID value, insert the PASID value into the command data, and send the command data to a device coupled to the processor. Other embodiments are described and claimed.

公开(公告)号：US20230153143A1

公开(公告)日：2023-05-18

申请号：US18097897

申请日：2023-01-17

Applicant: Intel Corporation

Inventor： SHAOPENG HE ,  ANJALI SINGHAI JAIN ,  UTKARSH Y. KAKAIYA ,  YADONG LI ,  ELIEL LOUZOUN ,  KUN TIAN ,  BRADLEY BURRES ,  RORY HARRIS ,  YAN ZHAO

IPC: G06F9/455 ,  G06F13/42

CPC classification number: G06F9/45558 ,  G06F13/4221 ,  G06F2009/45579 ,  G06F2213/0026

Abstract: Creating hybrid virtual devices using a plurality of physical functions. A processor of a device may identify a plurality of physical functions accessible to the device, the plurality of physical functions including a first physical function and a second physical function. The processor may create a virtual device to comprise the first physical function to provide a first capability and the second physical function to provide a second capability, wherein the first capability and second capability are different capabilities.

公开(公告)号：US20200327256A1

公开(公告)日：2020-10-15

申请号：US16912076

申请日：2020-06-25

Applicant: INTEL CORPORATION

Inventor： JOSHUA FENDER ,  UTKARSH Y. KAKAIYA ,  MOHAN NAIR ,  BRIAN MORRIS ,  PRATIK MAROLIA

IPC: G06F21/76 ,  H04L29/08 ,  G06F11/14 ,  G06F1/3206 ,  G06F21/54 ,  G06F1/324 ,  G06F21/74 ,  H04L29/06 ,  G06F1/20 ,  G06F1/3287

Abstract: Various embodiments are generally directed to securing systems that include hardware accelerators, such as FPGA-based accelerators, and privileged system components. Some embodiments may provide a security broker. In various embodiments, the security broker may provide interfaces between the hardware accelerator and the privileged component. Some embodiments may receive an instruction from the hardware accelerator targeting the privileged component, and validate the instruction based on a configuration. In some embodiments, upon determining the instruction is not validated, the instruction is restricted from further processing.

公开(公告)号：US20240345865A1

公开(公告)日：2024-10-17

申请号：US18643932

申请日：2024-04-23

Applicant: Intel Corporation

Inventor： SANJAY KUMAR ,  PHILIP R. LANTZ ,  KUN TIAN ,  UTKARSH Y. KAKAIYA ,  RAJESH M. SANKARAN

IPC: G06F9/455 ,  G06F9/30 ,  G06F12/1009

CPC classification number: G06F9/45558 ,  G06F9/30101 ,  G06F12/1009 ,  G06F2009/45579

Abstract: Techniques for transferring virtual machines and resource management in a virtualized computing environment are described. In one embodiment, for example, an apparatus may include at least one memory, at least one processor, and logic for transferring a virtual machine (VM), at least a portion of the logic comprised in hardware coupled to the at least one memory and the at least one processor, the logic to generate a plurality of virtualized capability registers for a virtual device (VDEV) by virtualizing a plurality of device-specific capability registers of a physical device to be virtualized by the VM, the plurality of virtualized capability registers comprising a plurality of device-specific capabilities of the physical device, determine a version of the physical device to support via a virtual machine monitor (VMM), and expose a subset of the virtualized capability registers associated with the version to the VM. Other embodiments are described and claimed.

公开(公告)号：US20230145856A1

公开(公告)日：2023-05-11

申请号：US18072368

申请日：2022-11-30

Applicant: INTEL CORPORATION

Inventor： JOSHUA FENDER ,  UTKARSH Y. KAKAIYA ,  MOHAN NAIR ,  BRAIN MORRIS ,  PRATIK MAROLIA

IPC: H04L67/562 ,  G06F11/14 ,  G06F1/3206 ,  G06F21/54 ,  G06F1/324 ,  G06F21/74 ,  H04L69/12 ,  G06F1/20

CPC classification number: H04L67/562 ,  G06F11/1441 ,  G06F1/3206 ,  G06F21/54 ,  G06F1/324 ,  G06F21/74 ,  H04L69/12 ,  G06F1/206 ,  G06F21/76

Abstract: Various embodiments are generally directed to securing systems that include hardware accelerators, such as FPGA-based accelerators, and privileged system components. Some embodiments may provide a security broker. In various embodiments, the security broker may provide interfaces between the hardware accelerator and the privileged component. Some embodiments may receive an instruction from the hardware accelerator targeting the privileged component, and validate the instruction based on a configuration. In some embodiments, upon determining the instruction is not validated, the instruction is restricted from further processing.

公开(公告)号：US20210406055A1

公开(公告)日：2021-12-30

申请号：US16911445

申请日：2020-06-25

Applicant: Intel Corporation

Inventor： UTKARSH Y. KAKAIYA ,  SANJAY K. KUMAR ,  PHILIP LANTZ ,  GILBERT NEIGER ,  RAJESH SANKARAN ,  VEDVYAS SHANBHOGUE

IPC: G06F9/455 ,  G06F9/30 ,  G06F9/50 ,  G06F9/54

Abstract: In one embodiment, a processor comprises: a first configuration register to store quality of service (QoS) information for a process address space identifier (PASID) value associated with a first process; and an execution circuit coupled to the first configuration register, where the execution circuit, in response to a first instruction, is to obtain command data from a first location identified in a source operand of the first instruction, insert the QoS information and the PASID value into the command data, and send a request comprising the command data to a device coupled to the processor, to enable the device to use the QoS information of a plurality of requests to manage sharing between a plurality of processes. Other embodiments are described and claimed.

公开(公告)号：US20210406022A1

公开(公告)日：2021-12-30

申请号：US16911441

申请日：2020-06-25

Applicant: Intel Corporation

Inventor： UTKARSH Y. KAKAIYA ,  RAJESH SANKARAN ,  GILBERT NEIGER ,  PHILIP LANTZ ,  SANJAY K. KUMAR

IPC: G06F9/34 ,  G06F9/30

Abstract: In one embodiment, a processor comprises: a first configuration register to store a pointer to a process address space identifier (PASID) table; and an execution circuit coupled to the first configuration register. The execution circuit, in response to a first instruction, is to obtain command data from a first location identified in a source operand of the first instruction, obtain a PASID table handle from the command data, access a first entry of the PASID table using the pointer from the first configuration register and the PASID table handle to obtain a PASID value, insert the PASID value into the command data, and send the command data to a device coupled to the processor. Other embodiments are described and claimed.