公开(公告)号：US20170289410A1

公开(公告)日：2017-10-05

申请号：US15085926

申请日：2016-03-30

Applicant: Intel Corporation

Inventor： Mohd Muhaiyiddin Bin Abdullah ,  Chee Kit Chew ,  Chung-Hao Chen

IPC: H04N5/213 ,  G06T5/20

CPC classification number: H04N5/213 ,  G06T5/20 ,  H01P1/20

Abstract: Techniques and mechanisms for exchanging image data via a three-wire data channel of an interconnect, at least a portion of which is disposed in or on a substrate of a printed circuit board. In an embodiment, three data signals are concurrently exchanged in parallel, each via a different respective trace portion of the data channel. The substrate has disposed therein or thereon three filter structures each to perform filtering of a different respective one of the three signals. The filter structures each include a respective sequence of corrugations to increase a stray capacitance provided by a substrate material. In another embodiment, the interconnect is compatible with a Mobile Industry Processor Interface (MIPI) camera physical layer interface (C-PHY) standard.

公开(公告)号：US20160173055A1

公开(公告)日：2016-06-16

申请号：US14569981

申请日：2014-12-15

Applicant: INTEL CORPORATION

Inventor： Michael W. Leddige ,  Wei Jern Tan ,  Chee Kit Chew ,  Natasya Athirah Abdul Khalid ,  Howard L. Heck

IPC: H03H7/38 ,  H01P3/08

CPC classification number: H05K1/025 ,  H05K2201/0979

Abstract: Techniques for impedance matching are described herein. The techniques include an apparatus for impedance matching including a trace section having a load impedance. The trace section comprises characteristics generating an impedance match between a main channel impedance and the load impedance.

Abstract translation: 本文描述了用于阻抗匹配的技术。 这些技术包括用于阻抗匹配的装置，其包括具有负载阻抗的迹线部分。 迹线部分包括在主通道阻抗和负载阻抗之间产生阻抗匹配的特性。