公开(公告)号：US20240170430A1

公开(公告)日：2024-05-23

申请号：US18515364

申请日：2023-11-21

申请人： X Display Company Technology Limited

发明人： Carl Prevatte ,  Christopher Bower ,  Ronald S. Cok ,  Matthew Meitl

IPC分类号： H01L23/00 ,  H01L21/48 ,  H05K1/11 ,  H05K3/30 ,  H05K3/34

CPC分类号： H01L24/11 ,  H01L24/08 ,  H01L24/13 ,  H01L24/14 ,  H01L24/17 ,  H05K1/112 ,  H05K3/3436 ,  H01L21/4803 ,  H01L21/4846 ,  H01L2224/1144 ,  H01L2224/11466 ,  H01L2224/13017 ,  H01L2224/13023 ,  H01L2224/1357 ,  H01L2224/1403 ,  H01L2224/1412 ,  H01L2224/1418 ,  H01L2224/16227 ,  H01L2224/1624 ,  H01L2224/17107 ,  H01L2924/12041 ,  H01L2924/12043 ,  H01L2924/12044 ,  H01L2924/1304 ,  H05K3/305 ,  H05K2201/09409 ,  H05K2201/09472 ,  H05K2201/0979 ,  H05K2201/10143

摘要： A component includes a plurality of electrical connections on a process side opposed to a back side of the component. Each electrical connection includes an electrically conductive multi-layer connection post protruding from the process side. A printed structure includes a destination substrate and one or more components. The destination substrate has two or more electrical contacts and each connection post is in contact with, extends into, or extends through an electrical contact of the destination substrate to electrically connect the electrical contacts to the connection posts. The connection posts or electrical contacts are deformed. Two or more connection posts can be electrically connected to a common electrical contact.

公开(公告)号：US20240008178A1

公开(公告)日：2024-01-04

申请号：US18253892

申请日：2021-10-29

申请人： NITTO DENKO CORPORATION

发明人： Shusaku SHIBATA ,  Takahiro IKEDA ,  Teppei NIINO

IPC分类号： H05K1/11 ,  H05K3/44

CPC分类号： H05K1/113 ,  H05K3/44 ,  H05K2201/09481 ,  H05K2201/09554 ,  H05K2201/09618 ,  H05K2201/09609 ,  H05K2201/0979 ,  H05K1/056

摘要： A wiring circuit board includes a metal supporting board; an insulating layer; and a conductive layer in this order in a thickness direction. The conductive layer includes a terminal portion, and a tail line portion extending from the terminal portion. The terminal portion has a via portion that penetrates the insulating layer in the thickness direction and is connected to the metal supporting board. The tail line portion has a base end portion that has a width different from a width of the terminal portion in a direction orthogonal to the extending direction of the tail line portion and that is connected with the terminal portion; and a second via portion that penetrates the insulating layer in the thickness direction and that is connected to the metal supporting board.

公开(公告)号：US11812554B2

公开(公告)日：2023-11-07

申请号：US17227458

申请日：2021-04-12

申请人： CHIPBOND TECHNOLOGY CORPORATION

发明人： Yu-Chen Ma ,  Hsin-Hao Huang ,  Wen-Fu Chou ,  Gwo-Shyan Sheu

IPC分类号： H05K1/11 ,  H05K1/18

CPC分类号： H05K1/118 ,  H05K1/189 ,  H05K2201/0979 ,  H05K2201/09445 ,  H05K2201/10674 ,  H05K2201/10734

摘要： A layout structure of flexible circuit board includes a flexible substrate, a chip and a circuit layer. A chip mounting area and a circuit area are defined on a top surface of the flexible substrate. The chip is mounted on the chip mounting area, a space exists between a first bump and a second bump of the chip, and there are no additional bumps between the first and second bumps. A first inner lead, a second inner lead, a first dummy lead and a second dummy lead of the circuit layer are located on the chip mounting area. The first and second inner leads are electrically connected to the first and second bumps respectively. The first dummy lead is connected to the first inner lead and adjacent to the first bump, and the second dummy lead is connected to the second inner lead and adjacent to the second bump.

公开(公告)号：US10017261B2

公开(公告)日：2018-07-10

申请号：US14650143

申请日：2013-12-02

申请人： ALENIA AERMACCHI S.P.A.

发明人： Marco Francesco Vercellesi

IPC分类号： H05B3/16 ,  B64D15/12 ,  H05B3/22 ,  H05K1/02 ,  F02K1/82 ,  H05B3/14 ,  H05B3/34 ,  B64D33/02

CPC分类号： B64D15/12 ,  B64D2033/0206 ,  B64D2033/0233 ,  F02K1/827 ,  H05B3/145 ,  H05B3/22 ,  H05B3/34 ,  H05B3/342 ,  H05B2203/007 ,  H05B2203/013 ,  H05B2203/014 ,  H05B2203/037 ,  H05B2214/02 ,  H05K1/0212 ,  H05K1/0296 ,  H05K1/0298 ,  H05K2201/09681 ,  H05K2201/0979 ,  Y02T50/672

摘要： An electronic circuit allows at least one current to flow between at least two points of the same circuit. The electronic circuit is in contact with a structure (P) and includes at least one graph (2) including a plurality of nodes (24) and a plurality of connections or branches (22) between the nodes (24) that create at least one mesh (M) of interconnections. The at least one mesh (M) includes interconnections that are configured at least two interconnections between two nodes (24) created by the plurality of connections or branches (22).

公开(公告)号：US20180192517A1

公开(公告)日：2018-07-05

申请号：US15854598

申请日：2017-12-26

申请人： Micron Technology, Inc.

发明人： Atsushi Morishima

IPC分类号： H05K1/11 ,  H05K1/18

CPC分类号： H05K1/115 ,  H05K1/025 ,  H05K1/114 ,  H05K1/181 ,  H05K2201/0776 ,  H05K2201/09227 ,  H05K2201/09309 ,  H05K2201/09609 ,  H05K2201/0979

摘要： Apparatuses and methods including conductive vias of a printed circuit board are described. An example apparatus includes a first layer including a first conductive plate; a component on the first layer, a second layer including a second conductive plate that may be coupled to an external power source; a third layer between the first layer and the second layer, the third layer including a third conductive plate; a first via coupling the first conductive plate to the second conductive plate; and a second via coupled to the first conductive plate. The first conductive plate includes a first portion coupled to the first via and the first conductive plate further includes a second portion coupled to the second via between the first portion and the component. The second via is coupled to either the second conductive plate or the third conductive plate.

公开(公告)号：US09997474B2

公开(公告)日：2018-06-12

申请号：US15477414

申请日：2017-04-03

申请人： SHINKO ELECTRIC INDUSTRIES CO., LTD.

发明人： Jun Furuichi ,  Noriyoshi Shimizu

IPC分类号： H01L23/00 ,  H01L21/48 ,  H05K1/02 ,  H01L21/56 ,  H01L23/498 ,  H01L23/31

CPC分类号： H01L23/562 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/16 ,  H01L2224/16227 ,  H01L2924/15313 ,  H01L2924/18161 ,  H01L2924/3511 ,  H05K1/0271 ,  H05K3/205 ,  H05K3/4682 ,  H05K2201/029 ,  H05K2201/0979 ,  H05K2201/10674

摘要： A wiring board includes a first insulating layer made of a single layer of non-photosensitive resin including a reinforcing member, a center position of the reinforcing member being positioned on a side toward a first surface with respect to a center of the first insulating layer in a thickness direction; a layered structure of a wiring layer and an insulating layer, stacked on the first surface of the first insulating layer; a through wiring provided to penetrate the first insulating layer, the through wiring and the first insulating layer forming a first concave portion at a second surface of the first insulating layer, in which the second end surface of the through wiring is exposed; and a pad for external connection formed at the second surface of the first insulating layer at a position corresponding to the through wiring and having a second concave portion.

公开(公告)号：US20180146551A1

公开(公告)日：2018-05-24

申请号：US15805480

申请日：2017-11-07

申请人： Hitoshi Kida

发明人： Hitoshi Kida

IPC分类号： H05K1/11 ,  H05K1/14 ,  B41J2/14

CPC分类号： H05K1/11 ,  B41J2/14201 ,  B41J2/14233 ,  B41J2002/14241 ,  B41J2002/14419 ,  B41J2002/14491 ,  H01L27/20 ,  H01L41/042 ,  H01L41/0475 ,  H01L41/0973 ,  H05K1/028 ,  H05K1/118 ,  H05K1/14 ,  H05K3/361 ,  H05K2201/09409 ,  H05K2201/09727 ,  H05K2201/0979

摘要： A wiring substrate includes a plurality of wiring patterns, a protective layer to cover the plurality of wiring patterns and regions between the plurality of wiring patterns, and a plurality of terminals communicating with the plurality of wiring patterns, respectively, the plurality of terminals not covered by the protective layer. Pitch between the plurality of terminals adjacent to each other includes a first pitch and a second pitch wider than the first pitch. At least one of the plurality of wiring patterns, the terminals of which are adjacent to each other at the second pitch, includes a portion of expanded width having a width wider than a width of the plurality of terminals. The portion of expanded width is covered with the protective layer.

公开(公告)号：US09930784B2

公开(公告)日：2018-03-27

申请号：US15208247

申请日：2016-07-12

申请人： SAMSUNG DISPLAY CO., LTD.

发明人： Dong Sun Lee

IPC分类号： H05K1/18 ,  H05K1/11 ,  H01L51/52 ,  G02F1/1345

CPC分类号： H05K1/181 ,  G02F1/13458 ,  H01L51/52 ,  H05K1/111 ,  H05K2201/09781 ,  H05K2201/0979 ,  H05K2201/10128 ,  Y02P70/611

摘要： A display device includes a substrate including a peripheral area with an integrated circuit chip disposed therein. A first pad portion, overlaps the integrated circuit chip, and includes a plurality of first dummy terminals, and a plurality of first connecting terminals electrically connected to the integrated circuit chip. The plurality of first dummy terminals is not electrically connected to the integrated circuit chip. A second pad portion, disposed in the peripheral area, includes a plurality of second connecting terminals electrically connected to a printed circuit board. A plurality of first connecting wires electrically connect each of the plurality of first connecting terminals to one or more of the plurality of second connecting terminals. At least one of the plurality of first connecting terminals is disposed between the plurality of first dummy terminals. The plurality of first connecting wires is not electrically connected to the plurality of first dummy terminals.

公开(公告)号：US09888574B1

公开(公告)日：2018-02-06

申请号：US15399664

申请日：2017-01-05

申请人： Micron Technology, Inc.

发明人： Atsushi Morishima

IPC分类号： H05K7/00 ,  H05K1/11 ,  H05K1/18

CPC分类号： H05K1/115 ,  H05K1/025 ,  H05K1/114 ,  H05K1/181 ,  H05K2201/0776 ,  H05K2201/09227 ,  H05K2201/09309 ,  H05K2201/09609 ,  H05K2201/0979

摘要： Apparatuses and methods including conductive vias of a printed circuit board are described. An example apparatus includes a first layer including a first conductive plate; a component on the first layer, a second layer including a second conductive plate that may be coupled to an external power source; a third layer between the first layer and the second layer, the third layer including a third conductive plate; a first via coupling the first conductive plate to the second conductive plate; and a second via coupled to the first conductive plate. The first conductive plate includes a first portion coupled to the first via and the first conductive plate further includes a second portion coupled to the second via between the first portion and the component. The second via is coupled to either the second conductive plate or the third conductive plate.

公开(公告)号：US20180035539A1

公开(公告)日：2018-02-01

申请号：US15650292

申请日：2017-07-14

申请人： FUJITSU TEN LIMITED

发明人： Tamaki Kawabata ,  Kenichi Osakabe

IPC分类号： H05K1/11 ,  H05K1/02 ,  H05K3/00

CPC分类号： H05K1/115 ,  H05K1/0209 ,  H05K1/0296 ,  H05K3/0088 ,  H05K3/0094 ,  H05K3/42 ,  H05K2201/094 ,  H05K2201/0979 ,  H05K2203/044

摘要： Provided is a printed circuit board structure that needs minimum manufacturing costs and in which there is little possibility that a solder bridge is formed. The printed circuit board structure is formed with via holes for electrically conductively connecting electrically conductive layers of a printed circuit board, and the via holes include a coated via hole with a land coated with solder resist and a non-coated via hole with a land not coated with solder resist, wherein the coated via hole is arranged in a place of the printed circuit board where a solder bridge or a solder ball is highly likely to be generated, and is electrically connected to at least one of the non-coated via hole in parallel.