公开(公告)号：US20240164018A1

公开(公告)日：2024-05-16

申请号：US18419212

申请日：2024-01-22

Applicant: DELL PRODUCTS L.P.

Inventor： Umesh CHANDRA ,  Douglas WALLACE ,  Bhyrav MUTNURY

IPC: H05K1/11 ,  H05K1/02

CPC classification number: H05K1/111 ,  H05K1/0215 ,  H05K1/025 ,  H05K2201/10318 ,  H05K2201/10636

Abstract: A high-speed transmission circuit comprises, as part of a signal path, a connector pin disposed on a pad that comprises an unused pad region. The unused pad region is not considered part of the signal path but is part of a resonant sub-circuit. In various embodiments, by properly adjusting the dimensions of the pad region and other structures in the high-speed transmission circuit, resonant frequencies of the sub-circuit are shifted to a frequency range that is outside of the frequency range of interest in the signal path, thereby, reducing insertion loss and increasing signal integrity without compromising mechanical stability.

公开(公告)号：US20240032196A1

公开(公告)日：2024-01-25

申请号：US18043356

申请日：2020-09-07

Applicant: GOERTEK TECHNOLOGY CO., LTD.

Inventor： Kenichiro KODAMA

IPC: H05K1/14 ,  H05K1/02

CPC classification number: H05K1/142 ,  H05K1/025 ,  H05K1/028 ,  H05K2201/10098 ,  H05K2201/10196 ,  H05K2201/10045

Abstract: An electronic device includes a first circuit operating on a first signal of a first frequency and a second circuit operating on a second signal of a second frequency. The first signal is different from the second signal, and the first circuit and the second circuit share a first component. The first component functions as an antenna for the second circuit, which reduces space occupied by a dedicated or independent antenna and achieves smaller size and better industrial design for the electronic device.

公开(公告)号：US20240030600A1

公开(公告)日：2024-01-25

申请号：US17872313

申请日：2022-07-25

Applicant: THE BOEING COMPANY

Inventor： Ted Dabrowski ,  Adriana Jara ,  Kalsi Kar Ning Kwan ,  John D. Williams

IPC: H01Q3/36 ,  H05K1/02 ,  H05K1/11

CPC classification number: H01Q3/36 ,  H05K1/028 ,  H05K1/0218 ,  H05K1/115 ,  H05K1/025 ,  H05K2201/10098

Abstract: A phased array antenna system includes a flexible printed circuit board formed of a flexible material. The flexible printed circuit board includes a component layer, an antenna layer, and a phase matching layer between the component layer and the antenna layer. A control unit is coupled to the component layer. A plurality of antenna elements are coupled to the antenna layer. A plurality of signal paths extend through the component layer, the phase matching layer, and the antenna layer. Each of the plurality of signal paths connects the control unit to a respective one of the plurality of antenna elements. The control unit provides an independent phase controllable source, which allows beams emitted from the antenna elements to be steered.

公开(公告)号：US20230369192A1

公开(公告)日：2023-11-16

申请号：US18226652

申请日：2023-07-26

Applicant: Intel Corporation

Inventor： Jonathan ROSCH ,  Wei-Lun JEN ,  Cheng XU ,  Liwei CHENG ,  Andrew BROWN ,  Yikang DENG

IPC: H01L23/498 ,  H01L21/48 ,  H05K1/11 ,  H05K1/02 ,  H05K1/18

CPC classification number: H01L23/49838 ,  H01L21/4857 ,  H01L23/49827 ,  H05K1/111 ,  H01L21/486 ,  H05K1/115 ,  H01L23/49822 ,  H05K2201/09727 ,  H05K1/025 ,  H05K2201/09736 ,  H05K2201/09827 ,  H05K1/18 ,  H05K2201/095

Abstract: Embodiments include a package substrate, a method of forming the package substrate, and a semiconductor package. A package substrate includes a conductive layer in a dielectric, a first trace and a first via pad of the conductive layer having a first thickness, and a second trace and a second via pad of the conductive layer having a second thickness. The second thickness of second trace and second via pad may be greater than the first thickness of the first trace and first via pad. The dielectric may include a first dielectric thickness and a second dielectric thickness, where the second dielectric thickness may be less than the first dielectric thickness. The package substrate may include a third via having a third thickness on the first via pad, and a fourth via having a fourth thickness on the second via pad, wherein the third thickness is greater than the fourth thickness.

公开(公告)号：US20230266363A1

公开(公告)日：2023-08-24

申请号：US18017128

申请日：2021-07-28

Applicant: KYOCERA Corporation

Inventor： Hitoshi TEGA

IPC: G01R1/073 ,  H05K1/02 ,  H05K1/11

CPC classification number: G01R1/07342 ,  H05K1/0298 ,  H05K1/119 ,  H05K1/025 ,  H05K2201/09609 ,  H05K2201/09672 ,  H05K2201/09445

Abstract: A circuit board includes an insulating substrate including a wiring conductor and a first resin substrate that is made of a resin different from the insulating substrate and is laminated on the insulating substrate. The first resin substrate has a plurality of internal conductors located from a surface thereof facing the insulating substrate to a surface on a side opposite to the insulating substrate. Each of the plurality of internal conductors includes a part that is inclined with respect to a perpendicular to the surface facing the insulating substrate. Intervals at which the plurality of internal conductors are located on the side opposite to the insulating substrate are narrower than intervals at which the plurality of internal conductors are located on an insulating substrate side.

公开(公告)号：US11696392B2

公开(公告)日：2023-07-04

申请号：US17008713

申请日：2020-09-01

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Kuniaki Yosui ,  Keiichi Hirose ,  Takahiro Baba

IPC: H05K1/02 ,  H01P3/08

CPC classification number: H05K1/025 ,  H01P3/08

Abstract: A transmission line includes connecting portion connected to the outside and a main body connected to the connecting portion. The connecting portion includes a terminal electrode connected to an external electrode, a signal conductor, and a ground conductor. The main body includes the signal conductor and the ground conductor. The connecting portion includes a first region including the terminal electrode, a second region adjacent to the first region along a signal transmission path, and a third region located between the second region and the main body. Impedance matching at the at least one of the connecting portions is achieved by the first region, the second region, and the third region.

公开(公告)号：US11653441B2

公开(公告)日：2023-05-16

申请号：US16951695

申请日：2020-11-18

Applicant: STMicroelectronics (Alps) SAS ,  STMicroelectronics (Grenoble 2) SAS

Inventor： Julien Didion ,  Thierry Lapergue

IPC: H05K1/02 ,  H04B1/16 ,  H05K1/18

CPC classification number: H05K1/025 ,  H04B1/16 ,  H05K1/181 ,  H05K2201/09272 ,  H05K2201/09281 ,  H05K2201/10045 ,  H05K2201/10098

Abstract: A device includes a printed circuit board substrate, an antenna connected to the printed circuit board substrate, an amplifier connected to the printed circuit board substrate, and a matching track having a first end electrically connected to an input of the amplifier and a second end electrically connected to an output of the antenna. The matching track has an outgrowth that is symmetrical along a median axis of the outgrowth. The matching track is rectilinear and has a constant width over an initial part extending between the widening area and the first end. A median axis of the initial part and the median axis of the outgrowth form an angle comprised between 60 and 120°.

公开(公告)号：US20190254158A1

公开(公告)日：2019-08-15

申请号：US16276140

申请日：2019-02-14

Applicant: EMC IP Holding Company, LLC

Inventor： Mickey S. Felton ,  Bhyrav M. Mutnury ,  Vijendera Kumar

IPC: H05K1/02 ,  H05K1/11

CPC classification number: H05K1/025 ,  H05K1/0243 ,  H05K1/111 ,  H05K2201/09418

Abstract: An electrical connector element, for use on a printed circuit board assembly, includes a soldering pad having a longitudinal length and a cross-sectional width. The soldering pad is configured to be electrically-coupleable to a PCB device conductor. At least one impedance inducing feature is positioned along the longitudinal length of the soldering pad.

公开(公告)号：US20180359848A1

公开(公告)日：2018-12-13

申请号：US15845463

申请日：2017-12-18

Applicant: Accton Technology Corporation

Inventor： Syue-Liang HONG

IPC: H05K1/02 ,  H05K1/18 ,  H05K1/11

CPC classification number: H05K1/0242 ,  H05K1/025 ,  H05K1/115 ,  H05K1/18

Abstract: A printed circuit board (PCB) for high-speed transmission is provided. The PCB includes: a plurality of circuit layers having one or more differential signal wires; a ground via, an anti-pad, and a signal via pair. The one or more differential signal wires have a first differential signal wire width on the plurality of circuit layers. The ground via provides a ground terminal to the plurality of circuit layers. The signal via pair is for connecting the plurality of circuit layers via a through-hole, so that the one or more differential signal wires pass through the anti-pad and pin through the plurality of circuit layers for signal transmission via the signal via pair. The one or more differential signal wires have a second differential signal wire width on the anti-pad, wherein the second differential signal wire width is greater than the first differential signal wire width.

公开(公告)号：US20180310397A1

公开(公告)日：2018-10-25

申请号：US15956945

申请日：2018-04-19

Applicant: Oclaro Japan, Inc.

Inventor： Daisuke NOGUCHI ,  Hiroshi YAMAMOTO

IPC: H05K1/02 ,  H05K3/10 ,  H01S5/022 ,  H05K1/18 ,  H05K1/14

CPC classification number: H05K1/025 ,  H01S5/02212 ,  H01S5/02276 ,  H01S5/06226 ,  H05K1/0274 ,  H05K1/141 ,  H05K1/189 ,  H05K3/103 ,  H05K3/3447 ,  H05K3/363 ,  H05K2201/10121 ,  H05K2203/049

Abstract: An optical subassembly includes: a conductor plate having a pair of penetration holes, both penetrating the conductor plate from an outer surface to an inner surface; a pair of lead terminals fixed in the two respective penetration holes and passing through the pair of penetration holes; a wiring board with a pair of wiring patterns arranged on a surface; and a plurality of bonding wires electrically connecting the pair of lead terminals and the pair of wiring patterns. A cross section of the pair of lead terminals on the inner surface side is larger than a cross section on the outer surface side. End faces on the inner surface side are situated within a range from +180 μm to −100 μm to the inner side from the inner surface of the conductor plate in a direction perpendicular to the inner surface.