公开(公告)号：US20160173055A1

公开(公告)日：2016-06-16

申请号：US14569981

申请日：2014-12-15

Applicant: INTEL CORPORATION

Inventor： Michael W. Leddige ,  Wei Jern Tan ,  Chee Kit Chew ,  Natasya Athirah Abdul Khalid ,  Howard L. Heck

IPC: H03H7/38 ,  H01P3/08

CPC classification number: H05K1/025 ,  H05K2201/0979

Abstract: Techniques for impedance matching are described herein. The techniques include an apparatus for impedance matching including a trace section having a load impedance. The trace section comprises characteristics generating an impedance match between a main channel impedance and the load impedance.

Abstract translation: 本文描述了用于阻抗匹配的技术。 这些技术包括用于阻抗匹配的装置，其包括具有负载阻抗的迹线部分。 迹线部分包括在主通道阻抗和负载阻抗之间产生阻抗匹配的特性。

公开(公告)号：US20250107003A1

公开(公告)日：2025-03-27

申请号：US18475920

申请日：2023-09-27

Applicant: Intel Corporation

Inventor： Chin Mian Choong ,  Jiun Hann Sir ,  Poh Boon Khoo ,  Wei Jern Tan ,  Boon Ping Koh

IPC: H05K1/18 ,  H01L23/498 ,  H01L25/18 ,  H05K1/14 ,  H05K3/40 ,  H05K3/46 ,  H10B80/00

Abstract: Systems, apparatus, articles of manufacture, and methods are disclosed comprising: an integrated circuit package including a package substrate, the package substrate including a first contact and a second contact, the first contact to be electrically coupled to a printed circuit board (PCB); and a timing package distinct from the integrated circuit package, the timing package including a third contact, the third contact to be electrically coupled to the second contact independent of the PCB.

公开(公告)号：US11239126B2

公开(公告)日：2022-02-01

申请号：US16487194

申请日：2017-03-31

Applicant: Intel Corporation

Inventor： Florence Su Sin Phun ,  Wei Jern Tan ,  Boon Ping Koh ,  Nik Mohamed Azeim Nik Zurin ,  Kai Chong Ng

IPC: H01L23/13 ,  H01L21/48 ,  H01L23/498 ,  H01L23/00 ,  H01L25/18

Abstract: An embodiment includes an apparatus comprising: a rod-shaped substrate including a rod long axis; a first layer, including a first interconnect, substantially surrounding the substrate in a first plane that is orthogonal to the rod long axis; and a second layer, including a second interconnect, substantially surrounding the first layer in the first plane. Other embodiments are described herein.

公开(公告)号：US20210074598A1

公开(公告)日：2021-03-11

申请号：US16487194

申请日：2017-03-31

Applicant: Intel Corporation

Inventor： Florence Su Sin Phun ,  Wei Jern Tan ,  Boon Ping Koh ,  Nik Mohamed Azeim Nik Zurin ,  Kai Chong Ng

IPC: H01L23/13 ,  H01L25/18 ,  H01L23/498 ,  H01L23/00 ,  H01L21/48

Abstract: An embodiment includes an apparatus comprising: a rod-shaped substrate including a rod long axis; a first layer, including a first interconnect, substantially surrounding the substrate in a first plane that is orthogonal to the rod long axis; and a second layer, including a second interconnect, substantially surrounding the first layer in the first plane. Other embodiments are described herein.

公开(公告)号：US20200187352A1

公开(公告)日：2020-06-11

申请号：US16662717

申请日：2019-10-24

Applicant: Intel Corporation

Inventor： Wei Jern Tan ,  Tony Lewis

IPC: H05K1/11 ,  H05K1/02

Abstract: To reduce the effect of undesirable electrical resonances in via stubs (e.g., portions of electrically conductive material in a via that form an open circuit by electrically connecting at only one end), a multi-layer printed circuit board can electrically connect traces in different layers using two vias that are electrically connected to each other. For example, a first electrical trace can electrically connect to a first via at a first layer, the first via can electrically connect to a second via at the topmost layer (or the bottommost layer), and the second via can electrically connect to a second electrical trace at a second layer. Compared to a typical single-via connection scheme, the two-via connection scheme can produce stubs that are shorter in length and therefore have an increased resonant frequency that may avoid interference with electrical signals sent through the first and second electrical traces.