公开(公告)号：US20220405234A1

公开(公告)日：2022-12-22

申请号：US17827882

申请日：2022-05-30

Applicant: Intel Corporation

Inventor： Vedvyas Shanbhogue ,  Stephen J. Robinson ,  Christopher D. Bryant ,  Jason W. Brandt

IPC: G06F15/80 ,  G06F9/30

Abstract: A processor includes a widest set of data registers that corresponds to a given logical processor. Each of the data registers of the widest set have a first width in bits. A decode unit that corresponds to the given logical processor is to decode instructions that specify the data registers of the widest set, and is to decode an atomic store to memory instruction. The atomic store to memory instruction is to indicate data that is to have a second width in bits that is wider than the first width in bits. The atomic store to memory instruction is to indicate memory address information associated with a memory location. An execution unit is coupled with the decode unit. The execution unit, in response to the atomic store to memory instruction, is to atomically store the indicated data to the memory location.

公开(公告)号：US20210406194A1

公开(公告)日：2021-12-30

申请号：US16914324

申请日：2020-06-27

Applicant: Intel Corporation

Inventor： Christopher D. Bryant

IPC: G06F12/1027

Abstract: Systems, methods, and apparatuses relating to circuitry to implement a pipelined out of order page miss handler are described. In one embodiment, a hardware processor core includes an execution circuit to generate data storage requests for virtual addresses, a translation lookaside buffer to translate the virtual addresses to physical addresses, and a single page miss handler circuit comprising a plurality of pipelined page walk stages, wherein the single page miss handler circuit is to contemporaneously perform a first page walk within a first stage of the plurality of pipelined page walk stages for a first miss of a first virtual address in the translation lookaside buffer, and a second page walk within a second stage of the plurality of pipelined page walk stages for a second miss of a second virtual address in the translation lookaside buffer.

公开(公告)号：US09921968B2

公开(公告)日：2018-03-20

申请号：US15396628

申请日：2016-12-31

Applicant: INTEL CORPORATION

Inventor： Christopher D. Bryant ,  Rama S. Gopal

IPC: G06F12/1036 ,  G06F12/1009

CPC classification number: G06F12/1009 ,  G06F12/084 ,  G06F12/1027 ,  G06F12/1036 ,  G06F2212/1016 ,  G06F2212/60 ,  G06F2212/62 ,  G06F2212/681 ,  G06F2212/684

Abstract: Methods and apparatus are disclosed for using a shared page miss handler device to satisfy page miss requests of a plurality of devices in a multi-core system. One embodiment of such a method comprises receiving one or more page miss requests from one or more respective requesting devices of the plurality of devices in the multi-core system, and arbitrating to identify a first page miss requests of the one or more requesting devices A page table walk is performed to generate a physical address responsive to the first page miss request. Then the physical address is sent to the corresponding requesting device, or a fault is signaled to an operating system for the corresponding requesting device responsive to the first page miss request.

公开(公告)号：US20240427728A1

公开(公告)日：2024-12-26

申请号：US18670721

申请日：2024-05-21

Applicant: Intel Corporation

Inventor： Vedvyas Shanbhogue ,  Stephen J. Robinson ,  Christopher D. Bryant ,  Jason W. Brandt

IPC: G06F15/80 ,  G06F9/30 ,  G06F9/38

Abstract: A processor includes a widest set of data registers that corresponds to a given logical processor. Each of the data registers of the widest set have a first width in bits. A decode unit that corresponds to the given logical processor is to decode instructions that specify the data registers of the widest set, and is to decode an atomic store to memory instruction. The atomic store to memory instruction is to indicate data that is to have a second width in bits that is wider than the first width in bits. The atomic store to memory instruction is to indicate memory address information associated with a memory location. An execution unit is coupled with the decode unit. The execution unit, in response to the atomic store to memory instruction, is to atomically store the indicated data to the memory location.

公开(公告)号：US20240054077A1

公开(公告)日：2024-02-15

申请号：US18494164

申请日：2023-10-25

Applicant: Intel Corporation

Inventor： Christopher D. Bryant

IPC: G06F12/1009

CPC classification number: G06F12/1009 ,  G06F2212/651

Abstract: Systems, methods, and apparatuses relating to circuitry to implement a pipelined out of order page miss handler are described. In one embodiment, a hardware processor core includes an execution circuit to generate data storage requests for virtual addresses, a translation lookaside buffer to translate the virtual addresses to physical addresses, and a single page miss handler circuit comprising a plurality of pipelined page walk stages, wherein the single page miss handler circuit is to contemporaneously perform a first page walk within a first stage of the plurality of pipelined page walk stages for a first miss of a first virtual address in the translation lookaside buffer, and a second page walk within a second stage of the plurality of pipelined page walk stages for a second miss of a second virtual address in the translation lookaside buffer.

公开(公告)号：US10067762B2

公开(公告)日：2018-09-04

申请号：US15201218

申请日：2016-07-01

Applicant: Intel Corporation

Inventor： Vikash Agarwal ,  Christopher D. Bryant ,  Jonathan D. Combs ,  Stephen J. Robinson

IPC: G06F9/30

Abstract: Apparatuses, methods, and systems relating to memory disambiguation are described. In one embodiment, a processor includes a decoder to decode an instruction into a decoded instruction, an execution unit to execute the decoded instruction, a retirement unit to retire an executed instruction in program order, and a memory disambiguation circuit to allocate an entry in a memory disambiguation table for a first load instruction that is to be flushed for a memory ordering violation, the entry comprising a counter value and an instruction pointer for the first load instruction.

公开(公告)号：US11822486B2

公开(公告)日：2023-11-21

申请号：US16914324

申请日：2020-06-27

Applicant: Intel Corporation

Inventor： Christopher D. Bryant

IPC: G06F12/1009

CPC classification number: G06F12/1009 ,  G06F2212/651

Abstract: Systems, methods, and apparatuses relating to circuitry to implement a pipelined out of order page miss handler are described. In one embodiment, a hardware processor core includes an execution circuit to generate data storage requests for virtual addresses, a translation lookaside buffer to translate the virtual addresses to physical addresses, and a single page miss handler circuit comprising a plurality of pipelined page walk stages, wherein the single page miss handler circuit is to contemporaneously perform a first page walk within a first stage of the plurality of pipelined page walk stages for a first miss of a first virtual address in the translation lookaside buffer, and a second page walk within a second stage of the plurality of pipelined page walk stages for a second miss of a second virtual address in the translation lookaside buffer.

公开(公告)号：US10901940B2

公开(公告)日：2021-01-26

申请号：US15089525

申请日：2016-04-02

Applicant: INTEL CORPORATION

Inventor： Vedvyas Shanbhogue ,  Stephen J. Robinson ,  Christopher D. Bryant ,  Jason W. Brandt

IPC: G06F9/30 ,  G06F15/80

Abstract: A processor includes a widest set of data registers that corresponds to a given logical processor. Each of the data registers of the widest set have a first width in bits. A decode unit that corresponds to the given logical processor is to decode instructions that specify the data registers of the widest set, and is to decode an atomic store to memory instruction. The atomic store to memory instruction is to indicate data that is to have a second width in bits that is wider than the first width in bits. The atomic store to memory instruction is to indicate memory address information associated with a memory location. An execution unit is coupled with the decode unit. The execution unit, in response to the atomic store to memory instruction, is to atomically store the indicated data to the memory location.

公开(公告)号：US09875187B2

公开(公告)日：2018-01-23

申请号：US14566390

申请日：2014-12-10

Applicant: INTEL CORPORATION

Inventor： Christopher D. Bryant ,  Stephen J. Robinson

IPC: G06F12/00 ,  G06F12/0855 ,  G06F12/0802 ,  G06F9/48

CPC classification number: G06F12/0857 ,  G06F9/48 ,  G06F12/0802 ,  G06F2212/1021 ,  G06F2212/1024 ,  G06F2212/281 ,  G06F2212/608 ,  G06F2212/65

Abstract: A first operation associated with a request for a page miss handler may be identified. A second operation associated with a current execution of the page miss handler may also be identified. An age of the first operation and an age of the second operation may be determined. The page miss handler may be interrupted based on the age of the first operation and the age of the second operation by stopping the current execution of the page miss handler for the second operation and starting execution of the page miss handler for the first operation.

公开(公告)号：US12007938B2

公开(公告)日：2024-06-11

申请号：US17827882

申请日：2022-05-30

Applicant: Intel Corporation

Inventor： Vedvyas Shanbhogue ,  Stephen J. Robinson ,  Christopher D. Bryant ,  Jason W. Brandt

IPC: G06F9/30 ,  G06F15/80

CPC classification number: G06F15/8007 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/30112

Abstract: A processor includes a widest set of data registers that corresponds to a given logical processor. Each of the data registers of the widest set have a first width in bits. A decode unit that corresponds to the given logical processor is to decode instructions that specify the data registers of the widest set, and is to decode an atomic store to memory instruction. The atomic store to memory instruction is to indicate data that is to have a second width in bits that is wider than the first width in bits. The atomic store to memory instruction is to indicate memory address information associated with a memory location. An execution unit is coupled with the decode unit. The execution unit, in response to the atomic store to memory instruction, is to atomically store the indicated data to the memory location.