公开(公告)号：US09292463B2

公开(公告)日：2016-03-22

申请号：US13627512

申请日：2012-09-26

Applicant: Intel Corporation

Inventor： David C. Estrada ,  Vincent J. Zimmer ,  Palsamy Sakthikumar

IPC: G06F13/00 ,  G06F13/40 ,  G06F9/44

CPC classification number: G06F9/4411 ,  G06F9/4406 ,  G06F13/26 ,  G06F13/4027

Abstract: Various embodiments are directed to creating multiple device blocks associated with hardware devices, arranging the device blocks in an order indicative of positions of the hardware devices in a hierarchy of buses and bridges, and enabling access to the multiple device blocks from an operating system. An apparatus comprises a processor circuit and storage storing instructions operative on the processor circuit to create a device table comprising multiple device blocks, each device block corresponding to one of multiple hardware devices accessible to the processor circuit, the device blocks arranged in an order indicative of relative positions of the hardware devices in a hierarchy of buses and at least one bridge device; enable access to the device table by an operating system; and execute a second sequence of instructions of the operating system operative on the processor circuit to access the device table. Other embodiments are described and claimed herein.

Abstract translation: 各种实施例涉及创建与硬件设备相关联的多个设备块，以指示总线和桥接器层级中的硬件设备的位置的顺序排列设备块，以及使得能够从操作系统访问多个设备块。 一种装置包括处理器电路和存储器，其存储指令，其操作在所述处理器电路上以创建包括多个设备块的设备表，每个设备块对应于所述处理器电路可访问的多个硬件设备之一，所述设备块以指示 硬件设备在总线和至少一个桥接设备层级中的相对位置; 使操作系统能够访问设备表; 并且执行在处理器电路上操作的操作系统的第二指令序列以访问设备表。 在此描述和要求保护的其它实施例。

公开(公告)号：US10002002B2

公开(公告)日：2018-06-19

申请号：US15076384

申请日：2016-03-21

Applicant: INTEL CORPORATION

Inventor： David C. Estrada ,  Vincent J. Zimmer ,  Palsamy Sakthikumar

IPC: G06F13/36 ,  G06F9/44 ,  G06F13/40 ,  G06F13/26

CPC classification number: G06F9/4411 ,  G06F9/4406 ,  G06F13/26 ,  G06F13/4027

Abstract: Various embodiments are directed to creating multiple device blocks associated with hardware devices, arranging the device blocks in an order indicative of positions of the hardware devices in a hierarchy of buses and bridges, and enabling access to the multiple device blocks from an operating system. An apparatus comprises a processor circuit and storage storing instructions operative on the processor circuit to create a device table comprising multiple device blocks, each device block corresponding to one of multiple hardware devices accessible to the processor circuit, the device blocks arranged in an order indicative of relative positions of the hardware devices in a hierarchy of buses and at least one bridge device; enable access to the device table by an operating system; and execute a second sequence of instructions of the operating system operative on the processor circuit to access the device table. Other embodiments are described and claimed herein.