公开(公告)号：US10146440B2

公开(公告)日：2018-12-04

申请号：US15385791

申请日：2016-12-20

Applicant: INTEL CORPORATION

Inventor： Peng Li ,  Anand S. Ramalingam ,  Jawad B. Khan ,  William K. Lui ,  Divya Narayanan ,  Sanjeev N. Trika

IPC: G06F3/06

Abstract: Provided are an apparatus, system and method for offloading collision check operations in a memory storage device to a collision check unit. A collision check unit includes a collision table including logical addresses for pending Input/Output (I/O) requests. An I/O request is received to a target logical address addressing a block of data in the non-volatile memory. The logical address is sent to the collision check unit. Resources to transfer data with respect to the transfer buffer to data for the I/O request are allocated in parallel while the collision check unit is determining whether the collision table includes the target logical address. The collision check unit determines whether the collision table includes the target logical address and returns indication of whether the collision table includes the target logical address indicating that current data for the target logical address is already in the transfer buffer.

公开(公告)号：US11079958B2

公开(公告)日：2021-08-03

申请号：US16383490

申请日：2019-04-12

Applicant: INTEL CORPORATION

Inventor： Divya Narayanan ,  Jawad B. Khan ,  Michael D. Nelson ,  Akshay G. Pethe

IPC: G06F3/06

Abstract: Provided are an apparatus, system and method for offloading data transfer operations between source and destination storage devices to a hardware accelerator. The hardware accelerator includes a memory space and control logic to receive, from a host processor, a command descriptor indicating at least one source storage device having transfer data to transfer to at least one destination storage device and a computational task to perform on the transfer data. The control logic sends read commands to the at least one source storage device to read the transfer data to at least one read buffer in the memory space and performs the computational task on the transfer data to produce modified transfer data. The control logic writes the modified transfer data to at least one write buffer in the memory space to cause the modified transfer data to be written to the at least one destination storage device.

公开(公告)号：US11604594B2

公开(公告)日：2023-03-14

申请号：US17390441

申请日：2021-07-30

Applicant: Intel Corporation

Inventor： Divya Narayanan ,  Jawad B. Khan ,  Michael D. Nelson ,  Akshay G. Pethe

IPC: G06F3/06

Abstract: Provided are an apparatus, system and method for offloading data transfer operations between source and destination storage devices to a hardware accelerator. The hardware accelerator includes a memory space and control logic to receive, from a host processor, a command descriptor indicating at least one source storage device having transfer data to transfer to at least one destination storage device and a computational task to perform on the transfer data. The control logic sends read commands to the at least one source storage device to read the transfer data to at least one read buffer in the memory space and performs the computational task on the transfer data to produce modified transfer data. The control logic writes the modified transfer data to at least one write buffer in the memory space to cause the modified transfer data to be written to the at least one destination storage device.