公开(公告)号：US10203888B2

公开(公告)日：2019-02-12

申请号：US14975150

申请日：2015-12-18

Applicant: Intel Corporation

Inventor： Sanjeev N. Trika ,  Anand S. Ramalingam

IPC: G06F11/00 ,  G06F3/06 ,  G06F1/26 ,  G06F11/20 ,  G06F11/14

Abstract: Technologies for performing a data copy operation on a data storage device include storing a copy token in a power-fail-safe data structure that identifies the source address and destination address of the data copy operation, updating an address table to indicate that the source and destination addresses are involved in the data copy operation, and notifying a host requesting that data copy operation that the data copy operation has been completed prior to performing the data copy operation. The host may subsequently perform other tasks while the data storage device completes the data copy operation. During the data copy operation, data access requests to the source or destination addresses are blocked based on the address table. Additionally, should a power failure event occur, the power-fail-safe data structure is saved to non-volatile data storage so that the copy operation may be completed upon the next power-on event of the data storage device.

公开(公告)号：US10146440B2

公开(公告)日：2018-12-04

申请号：US15385791

申请日：2016-12-20

Applicant: INTEL CORPORATION

Inventor： Peng Li ,  Anand S. Ramalingam ,  Jawad B. Khan ,  William K. Lui ,  Divya Narayanan ,  Sanjeev N. Trika

IPC: G06F3/06

Abstract: Provided are an apparatus, system and method for offloading collision check operations in a memory storage device to a collision check unit. A collision check unit includes a collision table including logical addresses for pending Input/Output (I/O) requests. An I/O request is received to a target logical address addressing a block of data in the non-volatile memory. The logical address is sent to the collision check unit. Resources to transfer data with respect to the transfer buffer to data for the I/O request are allocated in parallel while the collision check unit is determining whether the collision table includes the target logical address. The collision check unit determines whether the collision table includes the target logical address and returns indication of whether the collision table includes the target logical address indicating that current data for the target logical address is already in the transfer buffer.

公开(公告)号：US20160283338A1

公开(公告)日：2016-09-29

申请号：US14670705

申请日：2015-03-27

Applicant: Intel Corporation

Inventor： Anand S. Ramalingam

IPC: G06F11/22 ,  G06F11/14 ,  G06F9/44

CPC classification number: G06F11/2284 ,  G06F3/061 ,  G06F3/0632 ,  G06F3/0679 ,  G06F9/4411 ,  G06F9/442 ,  G06F11/1441

Abstract: Apparatus, systems, and methods to implement boot operations in nonvolatile storage devices are described. In one example, a controller comprises logic to receive a shutdown notification from a host device operating system, monitor modifications to one or more an indirection table segments for the nonvolatile memory during a shutdown process, and mark the one or more indirection table segments which were modified during the shutdown for fast loading during a subsequent boot process for the host device. Other examples are also disclosed and claimed.

Abstract translation: 描述了在非易失性存储设备中实现引导操作的装置，系统和方法。 在一个示例中，控制器包括从主机设备操作系统接收关闭通知的逻辑，在关闭过程期间监视对于非易失性存储器的一个或多个间接表段的修改，并且标记一个或多个间接表段， 在关闭期间修改，以便在主机设备的后续引导过程中进行快速加载。 还公开并要求保护其他实例。

公开(公告)号：US10114556B2

公开(公告)日：2018-10-30

申请号：US15723072

申请日：2017-10-02

Applicant: INTEL CORPORATION

Inventor： Anand S. Ramalingam

IPC: G06F12/00 ,  G06F3/06 ,  G06F12/02 ,  G06F12/0804

Abstract: A controller of a solid state drive initiates a repacking of data stored in a non-volatile memory of the solid state drive, wherein refreshing of the data stored in the non-volatile memory of the solid state drive is performed during the repacking of the data stored in the non-volatile memory of the solid state drive. Logical blocks are placed physically contiguously in an increasing order in pre-erased locations of the non-volatile memory of the solid state drive while the data stored in the non-volatile memory of the solid state drive is being repacked.

公开(公告)号：US09870462B2

公开(公告)日：2018-01-16

申请号：US14492168

申请日：2014-09-22

Applicant: Intel Corporation

Inventor： Sanjeev N. Trika ,  Jason Cox ,  Anand S. Ramalingam

IPC: G06F21/44 ,  H04L9/32 ,  G06F21/31

CPC classification number: G06F21/44 ,  G06F21/31 ,  G06F21/85 ,  G06F2221/2103 ,  H04L9/0894 ,  H04L9/3271

Abstract: Generally, this disclosure provides systems, devices, methods and computer readable media for prevention of cable swap security attacks on storage devices. A host system may include a provisioning module configured to generate a challenge-response verification key-pair and further to provide the key-pair to the storage device to enable the challenge-response verification. The system may also include a link error detection module to detect a link error between the host system and the storage device. The system may further include a challenge-response protocol module configured to initiate, in response to the link-error detection, a verification challenge from the storage system and to provide a response to the verification challenge based on the key-pair.

公开(公告)号：US20170177243A1

公开(公告)日：2017-06-22

申请号：US14975150

申请日：2015-12-18

Applicant: Intel Corporation

Inventor： Sanjeev N. Trika ,  Anand S. Ramalingam

IPC: G06F3/06 ,  G06F11/20 ,  G06F1/26

CPC classification number: G06F3/0619 ,  G06F1/26 ,  G06F3/0647 ,  G06F3/065 ,  G06F3/0685 ,  G06F11/1441 ,  G06F11/2015 ,  G06F11/2094 ,  G06F2201/805

Abstract: Technologies for performing a data copy operation on a data storage device include storing a copy token in a power-fail-safe data structure that identifies the source address and destination address of the data copy operation, updating an address table to indicate that the source and destination addresses are involved in the data copy operation, and notifying a host requesting that data copy operation that the data copy operation has been completed prior to performing the data copy operation. The host may subsequently perform other tasks while the data storage device completes the data copy operation. During the data copy operation, data access requests to the source or destination addresses are blocked based on the address table. Additionally, should a power failure event occur, the power-fail-safe data structure is saved to non-volatile data storage so that the copy operation may be completed upon the next power-on event of the data storage device.

公开(公告)号：US10126958B2

公开(公告)日：2018-11-13

申请号：US14875160

申请日：2015-10-05

Applicant: INTEL CORPORATION

Inventor： Anand S. Ramalingam

IPC: G06F3/06 ,  G06F12/02

Abstract: Techniques are disclosed for write suppression to improve endurance rating of non-volatile memories, such as QLC-NAND SSDs or other relatively slow, low endurance non-volatile memories. In an embodiment, an SSD is configured with a fast frontend non-volatile memory, a relatively slow lower endurance backend non-volatile memory, and a frontend manager that selectively transfers data from the fast memory to the slow memory based on transfer criteria. In operation, write data from the host is initially written to the fast memory by the frontend manager. The data is moved from the fast memory to the slow memory in bands. For each data band stored in the fast memory, the frontend manager tracks invalid data counts and data age. Only bands that still remain valid are transferred to the slow memory. After a given band has been fully transferred, it is erased and re-usable for other incoming writes by the frontend manager.

公开(公告)号：US20180089076A1

公开(公告)日：2018-03-29

申请号：US15278837

申请日：2016-09-28

Applicant: Intel Corporation

Inventor： Peng Li ,  Anand S. Ramalingam ,  William K. Lui ,  Sanjeev N. Trika

IPC: G06F12/02 ,  G11C14/00 ,  G06F3/06

CPC classification number: G06F12/0246 ,  G06F3/0616 ,  G06F3/0631 ,  G06F3/0644 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0665 ,  G06F3/0679 ,  G06F2212/1036 ,  G06F2212/152 ,  G06F2212/214 ,  G06F2212/651 ,  G06F2212/7201 ,  G06F2212/7202 ,  G06F2212/7203 ,  G11C14/0009

Abstract: Technologies for combining logical-to-physical address updates include a data storage device. The data storage device includes a non-volatile memory to store data and a logical to physical (L2P) table indicative of logical addresses and associated physical addresses of the data. Additionally, the data storage device includes a volatile memory to store one or more bins. Each bin is indicative of a subset of entries in the L2P table. Further, the data storage device includes a controller to allocate a bin in the volatile memory, write a plurality of updates to a subset of entries of the L2P table to the bin, and write the bin to the L2P table in a single write operation. Other embodiments are also described and claimed.

公开(公告)号：US09870169B2

公开(公告)日：2018-01-16

申请号：US14846102

申请日：2015-09-04

Applicant: INTEL CORPORATION

Inventor： Anand S. Ramalingam ,  Dale J. Juenemann ,  Pranav Kalavade

IPC: G11C11/56 ,  G06F3/06 ,  G06F12/0804 ,  G06F12/0868

CPC classification number: G06F3/0647 ,  G06F3/061 ,  G06F3/0685 ,  G06F12/0804 ,  G06F12/0868 ,  G06F2212/1032 ,  G06F2212/214 ,  G06F2212/225 ,  G06F2212/261 ,  G06F2212/7203 ,  G11C11/5628 ,  G11C2211/5648

Abstract: Techniques are disclosed for programming memory devices such as solid-state drives. In an embodiment, a memory controller is configured to execute a programming sequence that interleaves coarse and fine tuning steps for neighboring word lines. In one example, three consecutive word lines are programmed in six steps. At step 1, word line n is coarse programmed to an intermediate voltage level; at step 2, word line n+1 is coarse programmed to an intermediate voltage level; at step 3, word line n is fine programmed to its target voltage level; at step 4, word line n+2 is coarse programmed to an intermediate voltage level; at step 5, word line n+1 is fine programmed to its target voltage level; at step 6, word line n+2 is fine programmed to its target voltage level. No reads are allowed until all cell levels are programmed. Phase change memory may be used as staging buffer.

公开(公告)号：US20160284393A1

公开(公告)日：2016-09-29

申请号：US14671493

申请日：2015-03-27

Applicant: Intel Corporation

Inventor： Anand S. Ramalingam

IPC: G11C11/56 ,  G11C7/00

CPC classification number: G11C11/1675 ,  G06F12/0238 ,  G06F2212/7205 ,  G06F2212/7208 ,  G11C11/5628 ,  G11C13/0004 ,  G11C13/0035 ,  G11C13/0069 ,  G11C16/0483 ,  G11C16/3495 ,  G11C2211/5641 ,  G11C2213/71

Abstract: Methods and apparatus related to cost optimized Single Level Cell (SLC) write buffering for Three Level Cell (TLC) Solid State Drives (SSDs) are described. In one embodiment, non-volatile memory includes a first region in a Single Level Cell (SLC) mode and a second region in a multiple level cell mode. A portion of the second region is moved from the multiple level cell mode to the SLC mode, without adding any new capacity to the non-volatile memory and without reducing any existing capacity from the non-volatile memory. Other embodiments are also disclosed and claimed.

Abstract translation: 描述了与三电平（TLC）固态硬盘（SSD）的成本优化单电平（SLC）写缓冲相关的方法和设备。 在一个实施例中，非易失性存储器包括单级单元（SLC）模式中的第一区域和多级单元模式中的第二区域。 第二区域的一部分从多级单元模式移动到SLC模式，而不向非易失性存储器增加任何新的容量，并且不减少来自非易失性存储器的任何现有容量。 还公开并要求保护其他实施例。