公开(公告)号：US10528463B2

公开(公告)日：2020-01-07

申请号：US15278837

申请日：2016-09-28

Applicant: Intel Corporation

Inventor： Peng Li ,  Anand S. Ramalingam ,  William K. Lui ,  Sanjeev N. Trika

IPC: G06F12/02 ,  G06F3/06 ,  G11C14/00

Abstract: Technologies for combining logical-to-physical address updates include a data storage device. The data storage device includes a non-volatile memory to store data and a logical to physical (L2P) table indicative of logical addresses and associated physical addresses of the data. Additionally, the data storage device includes a volatile memory to store one or more bins. Each bin is indicative of a subset of entries in the L2P table. Further, the data storage device includes a controller to allocate a bin in the volatile memory, write a plurality of updates to a subset of entries of the L2P table to the bin, and write the bin to the L2P table in a single write operation. Other embodiments are also described and claimed.

公开(公告)号：US10146440B2

公开(公告)日：2018-12-04

申请号：US15385791

申请日：2016-12-20

Applicant: INTEL CORPORATION

Inventor： Peng Li ,  Anand S. Ramalingam ,  Jawad B. Khan ,  William K. Lui ,  Divya Narayanan ,  Sanjeev N. Trika

IPC: G06F3/06

Abstract: Provided are an apparatus, system and method for offloading collision check operations in a memory storage device to a collision check unit. A collision check unit includes a collision table including logical addresses for pending Input/Output (I/O) requests. An I/O request is received to a target logical address addressing a block of data in the non-volatile memory. The logical address is sent to the collision check unit. Resources to transfer data with respect to the transfer buffer to data for the I/O request are allocated in parallel while the collision check unit is determining whether the collision table includes the target logical address. The collision check unit determines whether the collision table includes the target logical address and returns indication of whether the collision table includes the target logical address indicating that current data for the target logical address is already in the transfer buffer.

公开(公告)号：US09564245B2

公开(公告)日：2017-02-07

申请号：US14141239

申请日：2013-12-26

Applicant: INTEL CORPORATION

Inventor： Bruce Querbach ,  Theodore Z. Schoenborn ,  David J. Zimmerman ,  David G. Ellis ,  Christopher W. Hampson ,  Ifar Wan ,  Yulan Zhang ,  Ramakrishna Mallela ,  William K. Lui

IPC: G06F11/263 ,  G06F11/27 ,  G11C11/406 ,  G11C29/00 ,  G11C29/36 ,  G11C29/44 ,  G11C29/10

CPC classification number: G11C29/36 ,  G06F11/263 ,  G06F11/27 ,  G11C11/406 ,  G11C29/10 ,  G11C29/4401 ,  G11C29/72 ,  G11C29/78 ,  G11C2029/4402

Abstract: In accordance with the present description, a device includes an internal defect detection and repair circuit which includes a self-test logic circuit built in within the device and a self-repair logic circuit also built in within the device. In one embodiment, the built in self-test logic circuit may be configured to automatically identify defective memory cells in a memory. Upon identifying one or more defective memory cells, the built in self-repair logic circuit may be configured to automatically repair the defective memory cells by replacing defective cells with spare cells within the memory.

公开(公告)号：US09922725B2

公开(公告)日：2018-03-20

申请号：US15368402

申请日：2016-12-02

Applicant: INTEL CORPORATION

Inventor： Bruce Querbach ,  William K. Lui ,  David G. Ellis ,  David J. Zimmerman ,  Theodore Z. Schoenborn ,  Christopher W. Hampson ,  Ifar Wan ,  Yulan Zhang

IPC: G11C29/44 ,  G11C29/36 ,  G11C29/18 ,  G11C29/16 ,  G11C29/12 ,  G11C29/00 ,  G06F11/27 ,  G06F11/263 ,  G11C29/38 ,  G11C29/10 ,  G11C29/20 ,  G11C11/406

CPC classification number: G11C29/38 ,  G06F11/263 ,  G06F11/27 ,  G11C11/406 ,  G11C29/10 ,  G11C29/1201 ,  G11C29/16 ,  G11C29/18 ,  G11C29/20 ,  G11C29/36 ,  G11C29/4401 ,  G11C29/72 ,  G11C29/78 ,  G11C29/783 ,  G11C2029/1202 ,  G11C2029/1204 ,  G11C2029/1206 ,  G11C2029/1208 ,  G11C2029/3602 ,  G11C2029/4402

Abstract: In accordance with the present description, a device includes an internal defect detection and repair circuit which includes a self-test logic circuit built in within the device and a self-repair logic circuit also built in within the device. In one embodiment, the built in self-test logic circuit may be configured to automatically identify defective memory cells in a memory. Upon identifying one or more defective memory cells, the built in self-repair logic circuit may be configured to automatically repair the defective memory cells by replacing defective cells with spare cells within the memory. In one embodiment, data patterns are generated as a function of memory addresses and periodic address offsets.

公开(公告)号：US09548137B2

公开(公告)日：2017-01-17

申请号：US14320164

申请日：2014-06-30

Applicant: INTEL CORPORATION

Inventor： Bruce Querbach ,  William K. Lui ,  David G. Ellis ,  David J. Zimmerman ,  Theodore Z. Schoenborn ,  Christopher W. Hampson ,  Ifar Wan ,  Yulan Zhang

IPC: G11C29/44 ,  G11C29/36 ,  G11C29/10 ,  G11C29/00 ,  G11C11/406 ,  G06F11/27 ,  G06F11/263

CPC classification number: G11C29/38 ,  G06F11/263 ,  G06F11/27 ,  G11C11/406 ,  G11C29/10 ,  G11C29/1201 ,  G11C29/16 ,  G11C29/18 ,  G11C29/20 ,  G11C29/36 ,  G11C29/4401 ,  G11C29/72 ,  G11C29/78 ,  G11C29/783 ,  G11C2029/1202 ,  G11C2029/1204 ,  G11C2029/1206 ,  G11C2029/1208 ,  G11C2029/3602 ,  G11C2029/4402

Abstract: In accordance with the present description, a device includes an internal defect detection and repair circuit which includes a self-test logic circuit built in within the device and a self-repair logic circuit also built in within the device. In one embodiment, the built in self-test logic circuit may be configured to automatically identify defective memory cells in a memory. Upon identifying one or more defective memory cells, the built in self-repair logic circuit may be configured to automatically repair the defective memory cells by replacing defective cells with spare cells within the memory.

Abstract translation: 根据本说明书，装置包括内部缺陷检测和修复电路，其包括内置于装置内的自检逻辑电路和内置在装置内的自修复逻辑电路。 在一个实施例中，内置自检逻辑电路可以被配置为自动识别存储器中的有缺陷的存储器单元。 在识别一个或多个有缺陷的存储器单元时，内置的自修复逻辑电路可以被配置为通过用存储器内的备用单元替换有缺陷的单元来自动修复有缺陷的存储器单元。

公开(公告)号：US10296224B2

公开(公告)日：2019-05-21

申请号：US15387600

申请日：2016-12-21

Applicant: INTEL CORPORATION

Inventor： Peng Li ,  William K. Lui ,  Sanjeev N. Trika

IPC: G06F3/06 ,  G06F12/10 ,  G06F12/02

Abstract: Provided are an apparatus, system and method for using a validity table indicating whether physical addresses have valid data to optimize write and defragmentation operations. A non-volatile memory storage device has non-volatile memory and a main memory. A memory controller reads and writes to the non-volatile memory and maintains in the main memory a logical-to-physical address table indicating, for each logical address of a plurality of logical addresses, a physical address in the non-volatile memory having data for the logical address. The main memory maintains a validity table indicating for each physical address of a plurality of physical addresses in the non-volatile memory whether the physical address has valid data.

公开(公告)号：US20180089076A1

公开(公告)日：2018-03-29

申请号：US15278837

申请日：2016-09-28

Applicant: Intel Corporation

Inventor： Peng Li ,  Anand S. Ramalingam ,  William K. Lui ,  Sanjeev N. Trika

IPC: G06F12/02 ,  G11C14/00 ,  G06F3/06

CPC classification number: G06F12/0246 ,  G06F3/0616 ,  G06F3/0631 ,  G06F3/0644 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0665 ,  G06F3/0679 ,  G06F2212/1036 ,  G06F2212/152 ,  G06F2212/214 ,  G06F2212/651 ,  G06F2212/7201 ,  G06F2212/7202 ,  G06F2212/7203 ,  G11C14/0009

Abstract: Technologies for combining logical-to-physical address updates include a data storage device. The data storage device includes a non-volatile memory to store data and a logical to physical (L2P) table indicative of logical addresses and associated physical addresses of the data. Additionally, the data storage device includes a volatile memory to store one or more bins. Each bin is indicative of a subset of entries in the L2P table. Further, the data storage device includes a controller to allocate a bin in the volatile memory, write a plurality of updates to a subset of entries of the L2P table to the bin, and write the bin to the L2P table in a single write operation. Other embodiments are also described and claimed.