公开(公告)号：US09710406B2

公开(公告)日：2017-07-18

申请号：US14570304

申请日：2014-12-15

Applicant: Intel Corporation

Inventor： Akshay G. Pethe ,  David J. Harriman ,  Mahesh Wagh ,  Abdul Hawk Ismail

IPC: G06F13/38 ,  G06F13/10 ,  G06F13/42 ,  G06F1/26 ,  G06F13/28 ,  G06F13/40

CPC classification number: G06F13/102 ,  G06F1/266 ,  G06F1/3203 ,  G06F13/287 ,  G06F13/387 ,  G06F13/4022 ,  G06F13/4221 ,  G06F13/4282

Abstract: Techniques for transmitted data through a USB port using a PCIe protocol are described herein. In one example, a method includes detecting a coupling of an apparatus and a PCIe compatible device via a Type-C connector and sending at least one vendor defined message to the PCIe compatible device. The method can also include receiving an alternate mode indicator corresponding to a data transfer via a PCIe protocol and sending an enter mode command to the PCIe compatible device to enable the data transfer between the apparatus and the PCIe compatible device via the PCIe protocol. Furthermore, the method can include transferring data between the apparatus and the PCIe compatible device via the Type-C connector with the PCIe protocol.

公开(公告)号：US20170177528A1

公开(公告)日：2017-06-22

申请号：US14978179

申请日：2015-12-22

Applicant: Intel Corporation

Inventor： David J. Harriman ,  Manjari Kulkarni ,  Akshay G. Pethe ,  Sean O. Stalley ,  Mahesh Wagh ,  Debendra Das Sharma

IPC: G06F13/40 ,  G06F13/36 ,  G06F13/42

CPC classification number: G06F13/4022 ,  G06F13/36 ,  G06F13/4282

Abstract: An interconnect switch is provided including switching logic executable to facilitate a Peripheral Component Interconnect Express (PCIe)-based interconnect, and further including a control host embedded in the switch to provide one or more enhanced routing capabilities. The control host includes a processor device, memory, and software executable by the processor device to process traffic received at one or more ports of the switch to redirect at least a portion of the traffic to provide the one or more enhanced routing capabilities.

公开(公告)号：US11079958B2

公开(公告)日：2021-08-03

申请号：US16383490

申请日：2019-04-12

Applicant: INTEL CORPORATION

Inventor： Divya Narayanan ,  Jawad B. Khan ,  Michael D. Nelson ,  Akshay G. Pethe

IPC: G06F3/06

Abstract: Provided are an apparatus, system and method for offloading data transfer operations between source and destination storage devices to a hardware accelerator. The hardware accelerator includes a memory space and control logic to receive, from a host processor, a command descriptor indicating at least one source storage device having transfer data to transfer to at least one destination storage device and a computational task to perform on the transfer data. The control logic sends read commands to the at least one source storage device to read the transfer data to at least one read buffer in the memory space and performs the computational task on the transfer data to produce modified transfer data. The control logic writes the modified transfer data to at least one write buffer in the memory space to cause the modified transfer data to be written to the at least one destination storage device.

公开(公告)号：US09952986B2

公开(公告)日：2018-04-24

申请号：US14986268

申请日：2015-12-31

Applicant: Intel Corporation

Inventor： Akshay G. Pethe ,  David J. Harriman ,  Mahesh Wagh ,  Abdul Hawk Ismail

IPC: G06F13/00 ,  G06F13/10 ,  G06F13/42 ,  G06F1/26 ,  G06F13/28 ,  G06F13/38 ,  G06F13/40 ,  G06F1/32

CPC classification number: G06F13/102 ,  G06F1/266 ,  G06F1/3203 ,  G06F13/287 ,  G06F13/387 ,  G06F13/4022 ,  G06F13/4221 ,  G06F13/4282

Abstract: Techniques for transmitted data through a USB port using a PCIe protocol are described herein. In one example, an apparatus includes a host controller, a root port, a multiplexor coupled to the host controller and the root port and a power delivery module. The power delivery module and the multiplexor can transmit and receive a request via a multimode input/output (I/O) interface and the power delivery module can detect a presence of an external device in response to the external device being coupled to the multimode I/O interface. The power delivery module can also send a first request to the external device to discover a vendor identifier of the external device, send a second request to discover at least one alternate mode supported by the external device, and send a third request to enable data transfer via the protocol.

公开(公告)号：US09306598B2

公开(公告)日：2016-04-05

申请号：US14193427

申请日：2014-02-28

Applicant: Intel Corporation

Inventor： Ilan Pardo ,  Ido Y. Soffair ,  Dror Reif ,  Debendra Das Sharma ,  Akshay G. Pethe

IPC: H03M7/00 ,  H03M7/30

CPC classification number: H03M7/6023 ,  H03M7/3088

Abstract: Method, apparatus, and systems employing dictionary-based high-bandwidth lossless compression. A pair of dictionaries having entries that are synchronized and encoded to support compression and decompression operations are implemented via logic at a compressor and decompressor. The compressor/decompressor logic operatives in a cooperative manner, including implementing the same dictionary update schemes, resulting in the data in the respective dictionaries being synchronized. The dictionaries are also configured with replaceable entries, and replacement policies are implemented based on matching bytes of data within sets of data being transferred over the link. Various schemes are disclosed for entry replacement, as well as a delayed dictionary update technique. The techniques support line-speed compression and decompression using parallel operations resulting in substantially no latency overhead.

Abstract translation: 使用基于字典的高带宽无损压缩的方法，装置和系统。 具有同步和编码以支持压缩和解压缩操作的条目的一对字典通过压缩器和解压缩器的逻辑来实现。 压缩器/解压缩器逻辑操作以协作的方式，包括实现相同的字典更新方案，导致相应词典中的数据被同步。 字典还配置有可替换条目，并且替换策略基于通过链接传送的数据集合中的数据的匹配字节来实现。 公开了用于条目替换的各种方案以及延迟字典更新技术。 该技术支持使用并行操作的线速压缩和解压缩，从而实质上无延迟开销。

公开(公告)号：US11604594B2

公开(公告)日：2023-03-14

申请号：US17390441

申请日：2021-07-30

Applicant: Intel Corporation

Inventor： Divya Narayanan ,  Jawad B. Khan ,  Michael D. Nelson ,  Akshay G. Pethe

IPC: G06F3/06

Abstract: Provided are an apparatus, system and method for offloading data transfer operations between source and destination storage devices to a hardware accelerator. The hardware accelerator includes a memory space and control logic to receive, from a host processor, a command descriptor indicating at least one source storage device having transfer data to transfer to at least one destination storage device and a computational task to perform on the transfer data. The control logic sends read commands to the at least one source storage device to read the transfer data to at least one read buffer in the memory space and performs the computational task on the transfer data to produce modified transfer data. The control logic writes the modified transfer data to at least one write buffer in the memory space to cause the modified transfer data to be written to the at least one destination storage device.

公开(公告)号：US10191877B2

公开(公告)日：2019-01-29

申请号：US14978179

申请日：2015-12-22

Applicant: Intel Corporation

Inventor： David J. Harriman ,  Manjari Kulkarni ,  Akshay G. Pethe ,  Sean O. Stalley ,  Mahesh Wagh ,  Debendra Das Sharma

IPC: G06F13/40 ,  G06F13/36 ,  G06F13/42

Abstract: An interconnect switch is provided including switching logic executable to facilitate a Peripheral Component Interconnect Express (PCIe)-based interconnect, and further including a control host embedded in the switch to provide one or more enhanced routing capabilities. The control host includes a processor device, memory, and software executable by the processor device to process traffic received at one or more ports of the switch to redirect at least a portion of the traffic to provide the one or more enhanced routing capabilities.

公开(公告)号：US20160170914A1

公开(公告)日：2016-06-16

申请号：US14986268

申请日：2015-12-31

Applicant: Intel Corporation

Inventor： Akshay G. Pethe ,  David J. Harriman ,  Mahesh Wagh ,  Abdul Hawk Ismail

IPC: G06F13/10 ,  G06F1/26 ,  G06F13/42

CPC classification number: G06F13/102 ,  G06F1/266 ,  G06F1/3203 ,  G06F13/287 ,  G06F13/387 ,  G06F13/4022 ,  G06F13/4221 ,  G06F13/4282

Abstract: Techniques for transmitted data through a USB port using a PCIe protocol are described herein. In one example, an apparatus includes a host controller, a root port, a multiplexor coupled to the host controller and the root port and a power delivery module. The power delivery module and the multiplexor can transmit and receive a request via a multimode input/output (I/O) interface and the power delivery module can detect a presence of an external device in response to the external device being coupled to the multimode I/O interface. The power delivery module can also send a first request to the external device to discover a vendor identifier of the external device, send a second request to discover at least one alternate mode supported by the external device, and send a third request to enable data transfer via the protocol.

Abstract translation: 本文描述了通过使用PCIe协议的USB端口传输的数据的技术。 在一个示例中，设备包括主机控制器，根端口，耦合到主控制器和根端口的多路复用器以及电源传递模块。 功率传递模块和多路复用器可以经由多模式输入/输出（I / O）接口发送和接收请求，并且功率传递模块可以响应外部设备耦合到多模I，检测外部设备的存在 / O接口。 电力传递模块还可以向外部设备发送第一请求以发现外部设备的供应商标识符，发送第二请求以发现由外部设备支持的至少一个替代模式，并且发送第三请求以启用数据传输 通过协议。

公开(公告)号：US10180927B2

公开(公告)日：2019-01-15

申请号：US15158265

申请日：2016-05-18

Applicant: Intel Corporation

Inventor： Akshay G. Pethe ,  Mahesh Wagh ,  Manjari Kulkarni

IPC: G06F13/40 ,  G06F13/42

Abstract: A device to process data packets for communication across PHY layers which are of different respective communication protocols. In an embodiment, the device includes a first protocol stack and a second protocol stack which are each for a PCIe™ communication protocol. The first protocol stack and a second protocol stack may interface, respectively, with a first physical (PHY) layer and a second PHY layer of the device. The first protocol stack and the second protocol stack may exchange packets to facilitate communications via both the first PHY layer and the second PHY layer. In another embodiment, the first PHY layer is for communication according to the PCIe™ communication protocol and the second PHY layer is for communication according to another, comparatively low power communication protocol.

公开(公告)号：US20160267048A1

公开(公告)日：2016-09-15

申请号：US15158265

申请日：2016-05-18

Applicant: Intel Corporation

Inventor： Akshay G. Pethe ,  Mahesh Wagh ,  Manjari Kulkarni

IPC: G06F13/42 ,  G06F13/40

CPC classification number: G06F13/4282 ,  G06F13/4027 ,  Y02D10/14 ,  Y02D10/151

Abstract: A device to process data packets for communication across PHY layers which are of different respective communication protocols. In an embodiment, the device includes a first protocol stack and a second protocol stack which are each for a PCIe™ communication protocol. The first protocol stack and a second protocol stack may interface, respectively, with a first physical (PHY) layer and a second PHY layer of the device. The first protocol stack and the second protocol stack may exchange packets to facilitate communications via both the first PHY layer and the second PHY layer. In another embodiment, the first PHY layer is for communication according to the PCIe™ communication protocol and the second PHY layer is for communication according to another, comparatively low power communication protocol.

Abstract translation: 用于处理数据分组以用于通过不同相应通信协议的PHY层进行通信的设备。 在一个实施例中，该设备包括第一协议栈和第二协议栈，它们各自用于PCIe TM通信协议。 第一协议栈和第二协议栈可分别与设备的第一物理（PHY）层和第二PHY层接口。 第一协议栈和第二协议栈可以交换分组以促进通过第一PHY层和第二PHY层的通信。 在另一个实施例中，第一PHY层用于根据PCIe TM通信协议进行通信，第二PHY层用于根据另一种较低功率通信协议进行通信。