公开(公告)号：US09507725B2

公开(公告)日：2016-11-29

申请号：US13729945

申请日：2012-12-28

Applicant: INTEL CORPORATION

Inventor： Steffen Kosinski ,  Fernando Latorre ,  Niranjan Cooray ,  Stanislav Shwartsman ,  Ethan Kalifon ,  Varun Mohandru ,  Pedro Lopez ,  Tom Aviram-Rosenfeld ,  Jaroslav Topp ,  Li-Gao Zei

IPC: G06F12/00 ,  G06F12/08

CPC classification number: G06F12/0895 ,  G06F12/0855 ,  G06F12/0866

Abstract: A bit or other vector may be used to identify whether an address range entered into an intermediate buffer corresponds to most recently updated data associated with the address range. A bit or other vector may also be used to identify whether an address range entered into an intermediate buffer overlaps with an address range of data that is to be loaded. A processing device may then determine whether to obtain data that is to be loaded entirely from a cache, entirely from an intermediate buffer which temporarily buffers data destined for a cache until the cache is ready to accept the data, or from both the cache and the intermediate buffer depending on the particular vector settings. Systems, devices, methods, and computer readable media are provided.

Abstract translation: 可以使用位或其他向量来识别输入中间缓冲器的地址范围是否对应于与地址范围相关联的最近更新的数据。 还可以使用位或其他向量来识别输入中间缓冲器的地址范围是否与要加载的数据的地址范围重叠。 然后，处理设备可以完全从中间缓冲区获得要从缓存中完全加载的数据，该中间缓冲器临时缓冲目的地为高速缓存的数据，直到高速缓存准备好接受数据，或者从高速缓存和 中间缓冲区取决于特定的向量设置。 提供了系统，设备，方法和计算机可读介质。