公开(公告)号：US09558121B2

公开(公告)日：2017-01-31

申请号：US13729840

申请日：2012-12-28

Applicant: INTEL CORPORATION

Inventor： Li-Gao Zei ,  Fernando Latorre ,  Steffen Kosinski ,  Jaroslaw Topp ,  Varun Mohandru ,  Lutz Naethke

IPC: G06F12/00 ,  G06F12/08 ,  G06F12/10

CPC classification number: G06F12/0846 ,  G06F12/0864 ,  G06F12/1063

Abstract: A virtually tagged cache may be configured to index virtual address entries in the cache into lockable sets based on a page offset value. When a memory operation misses on the virtually tagged cache, only the one set of virtual address entries with the same page offset may be locked. Thereafter, this general lock may be released and only an address stored in the physical tag array matching the physical address and a virtual address in the virtual tag array corresponding to the matching address stored in the physical tag array may be locked to reduce the amount and duration of locked addresses. The machine may be stalled only if a particular memory address request hits and/or tries to access one or more entries in a locked set. Devices, systems, methods, and computer readable media are provided.

Abstract translation: 虚拟标记的高速缓存可以被配置为基于页面偏移值将高速缓存中的虚拟地址条目索引到可锁定集合。 当内存操作错过虚拟标记的缓存时，只有一组具有相同页偏移量的虚拟地址条目可能被锁定。 此后，可以解除该通用锁定，并且仅锁定与物理地址匹配的物理标签阵列中存储的地址和与物理标签阵列中存储的匹配地址相对应的虚拟标签阵列中的虚拟地址，以减少数量和 锁定地址的持续时间。 只有当特定的存储器地址请求命中和/或尝试访问锁定集中的一个或多个条目时，才可能停止该机器。 提供了设备，系统，方法和计算机可读介质。

公开(公告)号：US09507725B2

公开(公告)日：2016-11-29

申请号：US13729945

申请日：2012-12-28

Applicant: INTEL CORPORATION

Inventor： Steffen Kosinski ,  Fernando Latorre ,  Niranjan Cooray ,  Stanislav Shwartsman ,  Ethan Kalifon ,  Varun Mohandru ,  Pedro Lopez ,  Tom Aviram-Rosenfeld ,  Jaroslav Topp ,  Li-Gao Zei

IPC: G06F12/00 ,  G06F12/08

CPC classification number: G06F12/0895 ,  G06F12/0855 ,  G06F12/0866

Abstract: A bit or other vector may be used to identify whether an address range entered into an intermediate buffer corresponds to most recently updated data associated with the address range. A bit or other vector may also be used to identify whether an address range entered into an intermediate buffer overlaps with an address range of data that is to be loaded. A processing device may then determine whether to obtain data that is to be loaded entirely from a cache, entirely from an intermediate buffer which temporarily buffers data destined for a cache until the cache is ready to accept the data, or from both the cache and the intermediate buffer depending on the particular vector settings. Systems, devices, methods, and computer readable media are provided.

Abstract translation: 可以使用位或其他向量来识别输入中间缓冲器的地址范围是否对应于与地址范围相关联的最近更新的数据。 还可以使用位或其他向量来识别输入中间缓冲器的地址范围是否与要加载的数据的地址范围重叠。 然后，处理设备可以完全从中间缓冲区获得要从缓存中完全加载的数据，该中间缓冲器临时缓冲目的地为高速缓存的数据，直到高速缓存准备好接受数据，或者从高速缓存和 中间缓冲区取决于特定的向量设置。 提供了系统，设备，方法和计算机可读介质。

公开(公告)号：US09195465B2

公开(公告)日：2015-11-24

申请号：US13729629

申请日：2012-12-28

Applicant: Intel Corporation

Inventor： Varun K. Mohandru ,  Fernando Latorre ,  Li-Gao Zei ,  Allan D. Knies ,  Rami May ,  Lutz Naethke

IPC: G06F9/38 ,  G06F12/08

CPC classification number: G06F9/3834 ,  G06F9/3842 ,  G06F9/3851 ,  G06F9/3863 ,  G06F12/0815 ,  G06F2212/507

Abstract: Responsive to execution of a computer instruction in a current translation window, state indicators associated with a cache line accessed for the execution may be modified. The state indicators may include: a first indicator to indicate whether the computer instruction is a load instruction moved from a subsequent translation window into the current translation window, a second indicator to indicate whether the cache line is modified in a cache responsive to the execution of the computer instruction, a third indicator to indicate whether the cache line is speculatively modified in the cache responsive to the execution of the computer instruction, a fourth indicator to indicate whether the cache line is speculatively loaded by the computer instruction, a fifth indicator to indicate whether a core executing the computer instruction exclusively owns the cache line, and a sixth indicator to indicate whether the cache line is invalid.

Abstract translation: 响应于在当前翻译窗口中执行计算机指令，可以修改与为执行访问的高速缓存行相关联的状态指示符。 状态指示符可以包括：第一指示符，用于指示计算机指令是否是从后续转换窗口移动到当前转换窗口的加载指令;第二指示符，用于指示高速缓存行是否在缓存中被修改，响应于执行 计算机指令，第三指示符，用于指示高速缓存行是否响应于计算机指令的执行在高速缓存中被推测地修改;第四指示符，用于指示高速缓存行是否被计算机指令推测性加载;第五指示符，用于指示 执行计算机指令的核心是否独占拥有高速缓存行，以及指示高速缓存行是否无效的第六指示符。

公开(公告)号：US09009413B2

公开(公告)日：2015-04-14

申请号：US13724848

申请日：2012-12-21

Applicant: Intel Corporation

Inventor： Varun K. Mohandru ,  Fernando Latorre ,  Niranjan L. Cooray ,  Pedro Lopez ,  Naveen Neelakantam ,  Li-Gao Zei ,  Rami May ,  Jaroslaw Topp ,  Thomas Gaertner

IPC: G06F12/08 ,  G11C7/10 ,  G06F12/10

CPC classification number: G11C7/1072 ,  G06F12/0804 ,  G06F12/0891 ,  G06F12/1036

Abstract: A processor includes a processor core including an execution unit to execute instructions, and a cache memory. The cache memory includes a controller to update each of a plurality of stale indicators in response to a lazy flush instruction. Each stale indicator is associated with respective data, and each updated stale indicator is to indicate that the respective data is stale. The cache memory also includes a plurality of cache lines. Each cache line is to store corresponding data and a foreground tag that includes a respective virtual address associated with the corresponding data, and that includes the associated stale indicator. Other embodiments are described as claimed.

Abstract translation: 处理器包括处理器核心，其包括执行指令的执行单元和高速缓冲存储器。 高速缓冲存储器包括控制器，以响应于惰性冲洗指令来更新多个陈旧指示器中的每一个。 每个陈旧的指示符与相应的数据相关联，每个更新的陈旧指示符指示相应的数据是否过时。 高速缓冲存储器还包括多条高速缓存行。 每个高速缓存行将存储对应的数据和前景标签，其包括与对应的数据相关联的相应的虚拟地址，并且其包括相关联的陈旧指示符。 其他实施例被描述为所要求保护的。