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    Cache coherency and processor consistency
    6.
    发明授权
    Cache coherency and processor consistency 有权
    缓存一致性和处理器一致性

    公开(公告)号：US09195465B2

    公开(公告)日：2015-11-24

    申请号：US13729629

    申请日：2012-12-28

    Applicant: Intel Corporation

    Inventor： Varun K. Mohandru ,  Fernando Latorre ,  Li-Gao Zei ,  Allan D. Knies ,  Rami May ,  Lutz Naethke

    IPC: G06F9/38 ,  G06F12/08

    CPC classification number: G06F9/3834 ,  G06F9/3842 ,  G06F9/3851 ,  G06F9/3863 ,  G06F12/0815 ,  G06F2212/507

    Abstract: Responsive to execution of a computer instruction in a current translation window, state indicators associated with a cache line accessed for the execution may be modified. The state indicators may include: a first indicator to indicate whether the computer instruction is a load instruction moved from a subsequent translation window into the current translation window, a second indicator to indicate whether the cache line is modified in a cache responsive to the execution of the computer instruction, a third indicator to indicate whether the cache line is speculatively modified in the cache responsive to the execution of the computer instruction, a fourth indicator to indicate whether the cache line is speculatively loaded by the computer instruction, a fifth indicator to indicate whether a core executing the computer instruction exclusively owns the cache line, and a sixth indicator to indicate whether the cache line is invalid.

    Abstract translation: 响应于在当前翻译窗口中执行计算机指令，可以修改与为执行访问的高速缓存行相关联的状态指示符。 状态指示符可以包括：第一指示符，用于指示计算机指令是否是从后续转换窗口移动到当前转换窗口的加载指令;第二指示符，用于指示高速缓存行是否在缓存中被修改，响应于执行 计算机指令，第三指示符，用于指示高速缓存行是否响应于计算机指令的执行在高速缓存中被推测地修改;第四指示符，用于指示高速缓存行是否被计算机指令推测性加载;第五指示符，用于指示 执行计算机指令的核心是否独占拥有高速缓存行，以及指示高速缓存行是否无效的第六指示符。

    Method and apparatus to implement lazy flush in a virtually tagged cache memory
    7.
    发明授权
    Method and apparatus to implement lazy flush in a virtually tagged cache memory 有权
    在虚拟标记的高速缓冲存储器中实现延迟刷新的方法和装置

    公开(公告)号：US09009413B2

    公开(公告)日：2015-04-14

    申请号：US13724848

    申请日：2012-12-21

    Applicant: Intel Corporation

    Inventor： Varun K. Mohandru ,  Fernando Latorre ,  Niranjan L. Cooray ,  Pedro Lopez ,  Naveen Neelakantam ,  Li-Gao Zei ,  Rami May ,  Jaroslaw Topp ,  Thomas Gaertner

    IPC: G06F12/08 ,  G11C7/10 ,  G06F12/10

    CPC classification number: G11C7/1072 ,  G06F12/0804 ,  G06F12/0891 ,  G06F12/1036

    Abstract: A processor includes a processor core including an execution unit to execute instructions, and a cache memory. The cache memory includes a controller to update each of a plurality of stale indicators in response to a lazy flush instruction. Each stale indicator is associated with respective data, and each updated stale indicator is to indicate that the respective data is stale. The cache memory also includes a plurality of cache lines. Each cache line is to store corresponding data and a foreground tag that includes a respective virtual address associated with the corresponding data, and that includes the associated stale indicator. Other embodiments are described as claimed.

    Abstract translation: 处理器包括处理器核心，其包括执行指令的执行单元和高速缓冲存储器。 高速缓冲存储器包括控制器，以响应于惰性冲洗指令来更新多个陈旧指示器中的每一个。 每个陈旧的指示符与相应的数据相关联，每个更新的陈旧指示符指示相应的数据是否过时。 高速缓冲存储器还包括多条高速缓存行。 每个高速缓存行将存储对应的数据和前景标签，其包括与对应的数据相关联的相应的虚拟地址，并且其包括相关联的陈旧指示符。 其他实施例被描述为所要求保护的。

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