公开(公告)号：US20150334114A1

公开(公告)日：2015-11-19

申请号：US14281651

申请日：2014-05-19

Applicant: INTEL CORPORATION

Inventor： VINCENT SCARLATA ,  SIMON JOHNSON ,  CARLOS ROZAS ,  FRANCIS MCKEEN ,  ITTAI ANATI ,  ILYA ALEXANDROVICH ,  REBEKAH LESLIE-HURD

IPC: H04L29/06

CPC classification number: G06F21/64 ,  G06F21/62 ,  G06F21/74 ,  G06F21/81 ,  G06F21/85 ,  H04L63/061 ,  H04L63/0876

Abstract: An apparatus and method for securely suspending and resuming the state of a processor. For example, one embodiment of a method comprises: generating a data structure including at least the monotonic counter value; generating a message authentication code (MAC) over the data structure using a first key; securely providing the data structure and the MAC to a module executed on the processor; the module verifying the MAC, comparing the monotonic counter value with a counter value stored during a previous suspend operation and, if the counter values match, then loading processor state required for the resume operation to complete. Another embodiment of a method comprises: generating a first key by a processor; securely sharing the first key with an off-processor component; and using the first key to generate a pairing ID usable to identify a pairing between the processor and the off-processor component.

Abstract translation: 一种用于安全地挂起并恢复处理器状态的装置和方法。 例如，方法的一个实施例包括：生成至少包括单调计数器值的数据结构; 使用第一密钥在数据结构上生成消息认证码（MAC）; 将数据结构和MAC安全地提供给在处理器上执行的模块; 所述模块验证所述MAC，将所述单调计数器值与在先前暂停操作期间存储的计数器值进行比较，并且如果所述计数器值匹配，则加载完成所述恢复操作所需的处理器状态。 方法的另一实施例包括：由处理器生成第一密钥; 用脱离处理器组件安全地共享第一个密钥; 以及使用所述第一密钥来生成可用于识别所述处理器和所述关闭处理器组件之间的配对的配对ID。

公开(公告)号：US20210200552A1

公开(公告)日：2021-07-01

申请号：US16728815

申请日：2019-12-27

Applicant: Intel Corporation

Inventor： FANGFEI LIU ,  CARLOS ROZAS ,  THOMAS UNTERLUGGAUER ,  FRANCIS MCKEEN ,  ALAA ALAMELDEEN ,  Abhishek Basak ,  XIANG ZOU ,  RON GABOR ,  JIYONG YU

IPC: G06F9/38

Abstract: An apparatus and method for non-speculative resource deallocation. For example, one embodiment of a processor comprises: front-end circuitry comprising branch prediction circuitry to indicate a speculative instruction path and a fetch unit to fetch instructions from a memory or instruction cache in accordance with the speculative instruction path; an in-order queue coupled to the front end circuitry, the in-order queue to store instructions of the speculative instruction path provided from the front end circuitry; an out-of-order cluster comprising first instruction processing resources including allocation circuitry to allocate execution resources to be used to execute the instructions of the speculative instruction path and an instruction dispatcher to perform out-of-order dispatching of the instructions for execution; back-end circuitry comprising a plurality of functional units to execute the instructions of the speculative instruction path, the plurality of functional units to perform out-of-order execution of the instructions; and in-order resource deallocation circuitry to deallocate the first instruction processing resources in program order.

公开(公告)号：US20220091851A1

公开(公告)日：2022-03-24

申请号：US17029335

申请日：2020-09-23

Applicant: Intel Corporation

Inventor： FANGFEI LIU ,  ALAA ALAMELDEEN ,  ABHISHEK BASAK ,  SCOTT CONSTABLE ,  FRANCIS MCKEEN ,  JOSEPH NUZMAN ,  CARLOS ROZAS ,  THOMAS UNTERLUGGAUER ,  XIANG ZOU

IPC: G06F9/38 ,  G06F9/48 ,  G06F21/54 ,  G06F9/30

Abstract: In one embodiment, a processor includes: a decode circuit to decode a load instruction that is to load an operand to a destination register, the decode circuit to generate at least one fencing micro-operation (μop) associated with the destination register; and a scheduler circuit coupled to the decode circuit. The scheduler circuit is to prevent speculative execution of one or more instructions that consume the operand in response to the at least one fencing μop. Other embodiments are described and claimed.

公开(公告)号：US20210200551A1

公开(公告)日：2021-07-01

申请号：US16728722

申请日：2019-12-27

Applicant: Intel Corporation

Inventor： CARLOS ROZAS ,  FRANCIS MCKEEN ,  PASQUALE COCCHINI ,  MELTEM OZSOY ,  MATTHEW FERNANDEZ

IPC: G06F9/38 ,  G06F9/30 ,  G06F9/50

Abstract: An apparatus and method for tracking speculative execution flow and detecting potential vulnerabilities. For example, one embodiment of a processor comprises: an instruction fetcher to fetch instructions from a cache or system memory; a branch predictor to speculate a first instruction path to be taken comprising a first sequence of instructions; a decoder to decode the first sequence of instructions; execution circuitry to execute the first sequence of instructions and process data associated with the instruction to generate results; information flow tracking circuitry and/or logic to: assign labels to all or a plurality of instructions in the first sequence of instructions, track resource usage of the plurality of instructions using the labels, merge sets of labels to remove redundancies; and responsive to detecting that the first instruction path was mis-predicted, generating one or more summaries comprising resources affected by one or more of the first sequence of instructions; and recycling labels responsive to retirement of instructions associated with the labels.