公开(公告)号：US10152451B2

公开(公告)日：2018-12-11

申请号：US15490743

申请日：2017-04-18

Applicant: Intel Corporation

Inventor： Zeev Sperber ,  Robert Valentine ,  Shlomo Raikin ,  Stanislav Shwartsman ,  Gal Ofir ,  Igor Yanover ,  Guy Patkin ,  Ofer Levy

IPC: G06F9/00 ,  G06F15/78 ,  G06F9/30 ,  G06F9/345 ,  G06F9/38

Abstract: Methods and apparatus are disclosed using an index array and finite state machine for scatter/gather operations. Embodiment of apparatus may comprise: decode logic to decode scatter/gather instructions and generate micro-operations. An index array holds a set of indices and a corresponding set of mask elements. A finite state machine facilitates the scatter operation. Address generation logic generates an address from an index of the set of indices for at least each of the corresponding mask elements having a first value. Storage is allocated in a buffer for each of the set of addresses being generated. Data elements corresponding to the set of addresses being generated are copied to the buffer. Addresses from the set are accessed to store data elements if a corresponding mask element has said first value and the mask element is changed to a second value responsive to completion of their respective stores.

公开(公告)号：US10146737B2

公开(公告)日：2018-12-04

申请号：US14616323

申请日：2015-02-06

Applicant: Intel Corporation

Inventor： Zeev Sperber ,  Robert Valentine ,  Guy Patkin ,  Stanislav Shwartsman ,  Shlomo Raikin ,  Igor Yanover ,  Gal Ofir

IPC: G06F9/00 ,  G06F15/80 ,  G06F9/30 ,  G06F9/38

Abstract: Methods and apparatus are disclosed for using an index array and finite state machine for scatter/gather operations. Embodiment of apparatus may comprise: decode logic to decode a scatter/gather instruction and generate a set of micro-operations, and an index array to hold a set of indices and a corresponding set of mask elements. A finite state machine facilitates the gather operation. Address generation logic generates an address from an index of the set of indices for at least each of the corresponding mask elements having a first value. An address is accessed to load a corresponding data element if the mask element had the first value. The data element is written at an in-register position in a destination vector register according to a respective in-register position the index. Values of corresponding mask elements are changed from the first value to a second value responsive to completion of their respective loads.

公开(公告)号：US20160103785A1

公开(公告)日：2016-04-14

申请号：US14881111

申请日：2015-10-12

Applicant: Intel Corporation

Inventor： Zeev Sperber ,  Robert Valentine ,  Guy Patkin ,  Stanislav Shwartsman ,  Shlomo Raikin ,  Igor Yanover ,  Gal Ofir

IPC: G06F15/80 ,  G06F9/30

CPC classification number: G06F15/8007 ,  G06F9/30018 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/30145 ,  G06F9/345 ,  G06F9/3887

Abstract: Methods and apparatus are disclosed for using an index array and finite state machine for scatter/gather operations. Embodiment of apparatus may comprise: decode logic to decode a scatter/gather instruction and generate a set of micro-operations, and an index array to hold a set of indices and a corresponding set of mask elements. A finite state machine facilitates the gather operation. Address generation logic generates an address from an index of the set of indices for at least each of the corresponding mask elements having a first value. An address is accessed to load a corresponding data element if the mask element had the first value. The data element is written at an in-register position in a destination vector register according to a respective in-register position the index. Values of corresponding mask elements are changed from the first value to a second value responsive to completion of their respective loads.

公开(公告)号：US09753889B2

公开(公告)日：2017-09-05

申请号：US14881111

申请日：2015-10-12

Applicant: Intel Corporation

Inventor： Zeev Sperber ,  Robert Valentine ,  Guy Patkin ,  Stanislav Shwartsman ,  Shlomo Raikin ,  Igor Yanover ,  Gal Ofir

IPC: G06F12/02 ,  G06F15/80 ,  G06F9/30 ,  G06F9/345

CPC classification number: G06F15/8007 ,  G06F9/30018 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/30145 ,  G06F9/345 ,  G06F9/3887

Abstract: Methods and apparatus are disclosed for using an index array and finite state machine for scatter/gather operations. Embodiment of apparatus may comprise: decode logic to decode a scatter/gather instruction and generate a set of micro-operations, and an index array to hold a set of indices and a corresponding set of mask elements. A finite state machine facilitates the gather operation. Address generation logic generates an address from an index of the set of indices for at least each of the corresponding mask elements having a first value. An address is accessed to load a corresponding data element if the mask element had the first value. The data element is written at an in-register position in a destination vector register according to a respective in-register position the index. Values of corresponding mask elements are changed from the first value to a second value responsive to completion of their respective loads.

公开(公告)号：US20170192934A1

公开(公告)日：2017-07-06

申请号：US14616323

申请日：2015-02-06

Applicant: Intel Corporation

Inventor： Zeev Sperber ,  Robert Valentine ,  Guy Patkin ,  Stanislav Shwartsman ,  Shlomo Raikin ,  Igor Yanover ,  Gal Ofir

IPC: G06F15/80 ,  G06F9/38 ,  G06F9/30

CPC classification number: G06F15/8007 ,  G06F9/30018 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/30145 ,  G06F9/345 ,  G06F9/3887

Abstract: Methods and apparatus are disclosed for using an index array and finite state machine for scatter/gather operations. Embodiment of apparatus may comprise: decode logic to decode a scatter/gather instruction and generate a set of micro-operations, and an index array to hold a set of indices and a corresponding set of mask elements. A finite state machine facilitates the gather operation. Address generation logic generates an address from an index of the set of indices for at least each of the corresponding mask elements having a first value. An address is accessed to load a corresponding data element if the mask element had the first value. The data element is written at an in-register position in a destination vector register according to a respective in-register position the index. Values of corresponding mask elements are changed from the first value to a second value responsive to completion of their respective loads.

公开(公告)号：US20150074373A1

公开(公告)日：2015-03-12

申请号：US13977727

申请日：2012-06-02

Applicant: INTEL CORPORATION

Inventor： Zeev Sperber ,  Robert Valentine ,  Shlomo Raikin ,  Stanislav Shwartsman ,  Gal Ofir ,  Igor Yanover ,  Guy Patkin ,  Levy Ofer

IPC: G06F15/78 ,  G06F9/30

CPC classification number: G06F15/7839 ,  G06F9/30018 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/30145 ,  G06F9/345 ,  G06F9/3808 ,  G06F9/383

Abstract: Methods and apparatus are disclosed using an index array and finite state machine for scatter/gather operations. Embodiment of apparatus may comprise: decode logic to decode scatter/gather instructions and generate micro-operations. An index array holds a set of indices and a corresponding set of mask elements. A finite state machine facilitates the scatter operation. Address generation logic generates an address from an index of the set of indices for at least each of the corresponding mask elements having a first value. Storage is allocated in a buffer for each of the set of addresses being generated. Data elements corresponding to the set of addresses being generated are copied to the buffer. Addresses from the set are accessed to store data elements if a corresponding mask element has said first value and the mask element is changed to a second value responsive to completion of their respective stores.

Abstract translation: 公开了使用索引阵列和有限状态机进行散射/收集操作的方法和装置。 设备的实施例可以包括：解码逻辑以解码散射/收集指令并产生微操作。 索引数组保存一组索引和一组对应的掩码元素。 有限状态机有助于散射操作。 地址生成逻辑从针对具有第一值的对应掩模元素中的至少每一个的索引集合的索引生成地址。 正在生成的每组地址的缓冲区中分配存储空间。 与生成的地址集相对应的数据元素被复制到缓冲器。 如果对应的掩码元素具有所述第一值并且掩模元素被响应于它们各自的存储的完成而被改变为第二值，则访问该集合的地址以存储数据元素。