公开(公告)号：US20180197789A1

公开(公告)日：2018-07-12

申请号：US15576396

申请日：2015-06-24

申请人： INTEL CORPORATION

发明人： GLENN A. GLASS ,  YING PANG ,  NABIL G. MISTKAWI ,  ANAND S. MURTHY ,  TAHIR GHANI ,  HUANG-LIN CHAO

IPC分类号： H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/161 ,  H01L29/20 ,  H01L29/10 ,  H01L29/08 ,  H01L21/8234 ,  H01L21/02 ,  H01L29/66

CPC分类号： H01L21/823807 ,  H01L21/02532 ,  H01L21/02546 ,  H01L21/823481 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/20 ,  H01L29/6681

摘要： Techniques are disclosed for customization of fin-based transistor devices to provide a diverse range of channel configurations and/or material systems, and within the same integrated circuit die. Sacrificial fins are removed via wet and/or dry etch chemistries configured to provide trench bottoms that are non-faceted and have no or otherwise low-ion damage. The trench is then filled with desired semiconductor material. A trench bottom having low-ion damage and non-faceted morphology encourages a defect-free or low defect interface between the substrate and the replacement material. In an embodiment, each of a first set of the sacrificial silicon fins is recessed and replaced with a p-type material, and each of a second set of the sacrificial fins is recessed and replaced with an n-type material. Another embodiment may include a combination of native fins (e.g., Si) and replacement fins (e.g., SiGe). Another embodiment may include replacement fins all of the same configuration.