公开(公告)号：US10248906B2

公开(公告)日：2019-04-02

申请号：US15392407

申请日：2016-12-28

Applicant: Intel Corporation

Inventor： Huseyin E. Sumbul ,  Gregory K. Chen ,  Raghavan Kumar ,  Phil Christopher Knag ,  Ram Krishnamurthy

IPC: G06F15/18 ,  G06N3/04 ,  G06N3/063 ,  G06N3/08

Abstract: A neuromorphic computing system is provided which comprises: a synapse core; and a pre-synaptic neuron, a first post-synaptic neuron, and a second post-synaptic neuron coupled to the synaptic core, wherein the synapse core is to: receive a request from the pre-synaptic neuron, generate, in response to the request, a first address of the first post-synaptic neuron and a second address of the second post-synaptic neuron, wherein the first address and the second address are not stored in the synapse core prior to receiving the request.

公开(公告)号：US20180189646A1

公开(公告)日：2018-07-05

申请号：US15396147

申请日：2016-12-30

Applicant: Intel Corporation

Inventor： Raghavan Kumar ,  Huseyin E. Sumbul ,  Gregory K. Chen ,  Phil Knag

IPC: G06N3/063

CPC classification number: G06N3/0635 ,  G06N3/049 ,  G06N3/063

Abstract: Apparatus and method for configuring large numbers of fan-in and fan-out connections in a neuromorphic computer. For example, one embodiment of an apparatus comprises: a plurality of neurons, each neuron uniquely identifiable with a neuron identifier (ID); at least one memory to store neuron addresses with wildcard values to establish fan-in and/or fan-out connections between the neurons; and a router to translate at least one neuron address containing wildcard values into two or more neuron IDs to establish the fan-in and/or fan-out connections between the neurons.

公开(公告)号：US10884957B2

公开(公告)日：2021-01-05

申请号：US16160952

申请日：2018-10-15

Applicant: Intel Corporation

Inventor： Amrita Mathuriya ,  Sasikanth Manipatruni ,  Victor W. Lee ,  Abhishek Sharma ,  Huseyin E. Sumbul ,  Gregory Chen ,  Raghavan Kumar ,  Phil Knag ,  Ram Krishnamurthy ,  Ian Young

IPC: G06F13/16 ,  G06F13/28 ,  G06N20/00

Abstract: Techniques and mechanisms for performing in-memory computations with circuitry having a pipeline architecture. In an embodiment, various stages of a pipeline each include a respective input interface and a respective output interface, distinct from said input interface, to couple to different respective circuitry. These stages each further include a respective array of memory cells and circuitry to perform operations based on data stored by said array. A result of one such in-memory computation may be communicated from one pipeline stage to a respective next pipeline stage for use in further in-memory computations. Control circuitry, interconnect circuitry, configuration circuitry or other logic of the pipeline precludes operation of the pipeline as a monolithic, general-purpose memory device. In other embodiments, stages of the pipeline each provide a different respective layer of a neural network.

公开(公告)号：US20190102669A1

公开(公告)日：2019-04-04

申请号：US15721653

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Gregory K. Chen ,  Kshitij Bhardwaj ,  Raghavan Kumar ,  Huseyin E. Sumbul ,  Phil Knag ,  Ram K. Krishnamurthy ,  Himanshu Kaul

IPC: G06N3/04 ,  G06N3/063

Abstract: In one embodiment, a processor comprises a first neuromorphic core to implement a plurality of neural units of a neural network, the first neuromorphic core comprising a memory to store a current time-step of the first neuromorphic core; and a controller to track current time-steps of neighboring neuromorphic cores that receive spikes from or provide spikes to the first neuromorphic core; and control the current time-step of the first neuromorphic core based on the current time-steps of the neighboring neuromorphic cores.

公开(公告)号：US11100385B2

公开(公告)日：2021-08-24

申请号：US15395758

申请日：2016-12-30

Applicant: Intel Corporation

Inventor： Raghavan Kumar ,  Gregory K. Chen ,  Huseyin E. Sumbul ,  Ram K. Krishnamurthy ,  Phil Knag

IPC: G06N3/04 ,  G06N3/063 ,  G06N3/08 ,  G06F7/58

Abstract: Apparatus and method for a scalable, free running neuromorphic processor. For example, one embodiment of a neuromorphic processing apparatus comprises: a plurality of neurons; an interconnection network to communicatively couple at least a subset of the plurality of neurons; a spike controller to stochastically generate a trigger signal, the trigger signal to cause a selected neuron to perform a thresholding operation to determine whether to issue a spike signal.

公开(公告)号：US20190042909A1

公开(公告)日：2019-02-07

申请号：US15821123

申请日：2017-11-22

Applicant: Intel Corporation

Inventor： Huseyin E. Sumbul ,  Gregory K. Chen ,  Phil Knag ,  Raghavan Kumar ,  Ram K. Krishnamurthy

IPC: G06N3/04 ,  G06N3/063

Abstract: In one embodiment, a processor comprises a first neuro-synaptic core comprising first circuitry to configure the first neuro-synaptic core as a neuron core responsive to a first value specified by a configuration parameter; and configure the first neuro-synaptic core as a synapse core responsive to a second value specified by the configuration parameter.

公开(公告)号：US11195079B2

公开(公告)日：2021-12-07

申请号：US15821123

申请日：2017-11-22

Applicant: INTEL CORPORATION

Inventor： Huseyin E. Sumbul ,  Gregory K. Chen ,  Phil Knag ,  Raghavan Kumar ,  Ram K. Krishnamurthy

IPC: G06N3/04 ,  G06N3/063 ,  G06N3/08 ,  G06N3/06

Abstract: In one embodiment, a processor comprises a first neuro-synaptic core comprising first circuitry to configure the first neuro-synaptic core as a neuron core responsive to a first value specified by a configuration parameter; and configure the first neuro-synaptic core as a synapse core responsive to a second value specified by the configuration parameter.

公开(公告)号：US11157799B2

公开(公告)日：2021-10-26

申请号：US16299014

申请日：2019-03-11

Applicant: Intel Corporation

Inventor： Huseyin E. Sumbul ,  Gregory K. Chen ,  Raghavan Kumar ,  Phil Christopher Knag ,  Ram Krishnamurthy

IPC: G06E1/00 ,  G06N3/04 ,  G06N3/063 ,  G06N3/08

Abstract: A neuromorphic computing system is provided which comprises: a synapse core; and a pre-synaptic neuron, a first post-synaptic neuron, and a second post-synaptic neuron coupled to the synaptic core, wherein the synapse core is to: receive a request from the pre-synaptic neuron, generate, in response to the request, a first address of the first post-synaptic neuron and a second address of the second post-synaptic neuron, wherein the first address and the second address are not stored in the synapse core prior to receiving the request.

公开(公告)号：US20170286829A1

公开(公告)日：2017-10-05

申请号：US15088198

申请日：2016-04-01

Applicant: Intel Corporation

Inventor： Gregory K. Chen ,  Raghavan Kumar ,  Huseyin E. Sumbul

IPC: G06N3/08 ,  G06N3/063

CPC classification number: G06N3/049 ,  G06N3/063 ,  G06N3/088

Abstract: Systems and methods for event-driven learning with spike timing dependent plasticity in neuromorphic computers are disclosed. A neuromorphic processor includes a synapse coupled to a pre-synaptic neuron and coupled to a post-synaptic neuron, the synapse including a synapse memory to store a synapse weight and synapse spike timing dependent plasticity (STDP) circuit coupled to the synapse memory. The pre-synaptic neuron includes a pre-synaptic neuron memory to store a pre-synaptic neuron spike history and a pre-synaptic neuron STDP circuit coupled to the pre-synaptic neuron memory, the pre-synaptic neuron STDP circuit to, in response to the pre-synaptic neuron firing, initiate performing long term potentiation. The post-synaptic neuron includes a post-synaptic neuron memory storing a post-synaptic neuron spike history and a post-synaptic neuron STDP circuit coupled to the post-synaptic neuron memory to, in response to the post-synaptic neuron firing, initiate performing long term depression.