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    TIME AND FREQUENCY DOMAIN SIDE-CHANNEL LEAKAGE SUPPRESSION USING INTEGRATED VOLTAGE REGULATOR CASCADED WITH RUNTIME CRYPTO ARITHMETIC TRANSFORMATIONS
    5.
    发明申请
    TIME AND FREQUENCY DOMAIN SIDE-CHANNEL LEAKAGE SUPPRESSION USING INTEGRATED VOLTAGE REGULATOR CASCADED WITH RUNTIME CRYPTO ARITHMETIC TRANSFORMATIONS 有权

    公开(公告)号：US20220200784A1

    公开(公告)日：2022-06-23

    申请号：US17132365

    申请日：2020-12-23

    申请人： Intel Corporation

    发明人： Raghavan Kumar ,  Xiaosen Liu ,  Harish Krishnamurthy ,  Sanu Mathew ,  Vikram Suresh

    IPC分类号： H04L9/00 ,  G06F1/26 ,  H04L9/06

    摘要： Apparatus and method for resisting side-channel attacks on cryptographic engines are described herein. An apparatus embodiment includes a cryptographic block coupled to a non-linear low-dropout voltage regulator (NL-LDO). The NL-LDO includes a scalable power train to provide a variable load current to the cryptographic block, randomization circuitry to generate randomized values for setting a plurality of parameters, and a controller to adjust the variable load current provided to the cryptographic block based on the parameters and the current voltage of the cryptographic block. The controller to cause a decrease in the variable load current when the current voltage is above a high voltage threshold, an increase in the variable load current when the current voltage is below a low voltage threshold; and a maximization of the variable load current when the current voltage is below an undervoltage threshold. The cryptographic block may be implemented with arithmetic transformations.

    Programmable neuron core with on-chip learning and stochastic time step control
    6.
    发明授权
    Programmable neuron core with on-chip learning and stochastic time step control 有权

    公开(公告)号：US11281963B2

    公开(公告)日：2022-03-22

    申请号：US15276111

    申请日：2016-09-26

    申请人： INTEL CORPORATION

    发明人： Raghavan Kumar ,  Gregory K. Chen ,  Huseyin Ekin Sumbul ,  Phil Knag

    IPC分类号： G06N3/04 ,  G06N3/063 ,  G06N3/08

    摘要： An integrated circuit (IC), as a computation block of a neuromorphic system, includes a time step controller to activate a time step update signal for performing a time-multiplexed selection of a group of neuromorphic states to update. The IC includes a first circuitry to, responsive to detecting the time step update signal for a selected group of neuromorphic states: generate an outgoing data signal in response to determining that a first membrane potential of the selected group of neuromorphic states exceeds a threshold value, wherein the outgoing data signal includes an identifier that identifies the selected group of neuromorphic states and a memory address (wherein the memory address corresponds to a location in a memory block associated with the integrated circuit), and update a state of the selected group of neuromorphic states in response to generation of the outgoing data signal.

    Device, system, and method to change a consistency of behavior by a cell circuit
    9.
    发明授权
    Device, system, and method to change a consistency of behavior by a cell circuit 有权

    公开(公告)号：US10825511B2

    公开(公告)日：2020-11-03

    申请号：US16417538

    申请日：2019-05-20

    申请人： Intel Corporation

    发明人： Vivek De ,  Sanu Mathew ,  Sudhir Satpathy ,  Vikram Suresh ,  Raghavan Kumar

    IPC分类号： G11C11/419 ,  H04L9/32 ,  G09G5/00 ,  G06F7/58

    摘要： Techniques and mechanisms for changing a consistency with which a cell circuit (“cell”) settles into a given state. In one embodiment, a cell settles into a preferred state based on a relative polarity between respective voltages of a first rail and a second rail. Based on the preferred state, a hot carrier injection (HCI) stress is applied to change a likelihood of the cell settling into the preferred state. Applying the HCI stress includes driving off-currents of two PMOS transistors of the cell while the relative polarity is reversed. In another embodiment, a cell array comprises multiple cells which are each classified as being a respective one of a physically unclonable function (PUF) type or a random number generator (RNG) type. A cell is selected for biasing, and a stress is applied, based on each of: that cell's preferred state, that cell's classification, and another cell's classification.

    Programmable interface to in-memory cache processor
    10.
    发明授权
    Programmable interface to in-memory cache processor 有权

    公开(公告)号：US10705967B2

    公开(公告)日：2020-07-07

    申请号：US16160270

    申请日：2018-10-15

    申请人： Intel Corporation

    发明人： Amrita Mathuriya ,  Sasikanth Manipatruni ,  Victor Lee ,  Huseyin Sumbul ,  Gregory Chen ,  Raghavan Kumar ,  Phil Knag ,  Ram Krishnamurthy ,  Ian Young ,  Abhishek Sharma

    IPC分类号： G06F12/0875 ,  G06N3/063 ,  G06N3/04 ,  G06F3/06 ,  G06F8/41 ,  G06F9/455

    摘要： The present disclosure is directed to systems and methods of implementing a neural network using in-memory mathematical operations performed by pipelined SRAM architecture (PISA) circuitry disposed in on-chip processor memory circuitry. A high-level compiler may be provided to compile data representative of a multi-layer neural network model and one or more neural network data inputs from a first high-level programming language to an intermediate domain-specific language (DSL). A low-level compiler may be provided to compile the representative data from the intermediate DSL to multiple instruction sets in accordance with an instruction set architecture (ISA), such that each of the multiple instruction sets corresponds to a single respective layer of the multi-layer neural network model. Each of the multiple instruction sets may be assigned to a respective SRAM array of the PISA circuitry for in-memory execution. Thus, the systems and methods described herein beneficially leverage the on-chip processor memory circuitry to perform a relatively large number of in-memory vector/tensor calculations in furtherance of neural network processing without burdening the processor circuitry.