公开(公告)号：US10096612B2

公开(公告)日：2018-10-09

申请号：US14853783

申请日：2015-09-14

Applicant: INTEL CORPORATION

Inventor： Sri Sai Sivakumar Vegunta ,  Gowrisankar Damarla ,  Jian Zhou

IPC: G06F12/00 ,  H01L27/11582 ,  H01L27/11573 ,  H01L21/3213 ,  H01L21/311 ,  H01L21/768 ,  G06F3/06 ,  H01L27/1157

Abstract: A three dimensional memory device is described having an array region and a periphery region. The array region has a three dimensional stack of storage cells. The periphery region has contacts that extend from above the three dimensional stack of storage cells to below the three dimensional stack of storage cells. The periphery region is substantially devoid of conducting and/or semi-conducting layers of the three dimensional stack of storage cells.