公开(公告)号：US09857989B1

公开(公告)日：2018-01-02

申请号：US15283296

申请日：2016-10-01

Applicant: Intel Corporation

Inventor： Jun Zhao ,  Gowrisankar Damarla ,  David A. Daycock ,  Gordon A. Haller ,  Sri Sai Sivakumar Vegunta ,  John B. Matovu ,  Matthew R. Park ,  Prakash Rau Mokhna Rau

IPC: G11C16/06 ,  G06F3/06

CPC classification number: G06F3/061 ,  G06F3/0655 ,  G06F3/0688 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582

Abstract: A solid state memory component can include a plurality of bit lines, a source line, and a plurality of non-functional memory pillars. Each non-functional memory pillar is electrically isolated from one or both of the plurality of bit lines and the source line. A solid state memory component can also include a plurality of pillars located in a periphery portion of the solid state memory component, and memory cells adjacent to each of the pillars. Associated systems and methods can include or otherwise utilize such solid state memory components.

公开(公告)号：US11010058B2

公开(公告)日：2021-05-18

申请号：US16436917

申请日：2019-06-11

Applicant: Intel Corporation

Inventor： Jun Zhao ,  Gowrisankar Damaria ,  David A. Daycock ,  Gordon A. Haller ,  Sri Sai Sivakumar Vegunta ,  John B. Matovu ,  Matthew R. Park ,  Prakash Rau Mokhna Rau

IPC: G06F3/06 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582 ,  H01L27/11565

Abstract: A solid state memory component can include a plurality of bit lines, a source line, and a plurality of non-functional memory pillars. Each non-functional memory pillar is electrically isolated from one or both of the plurality of bit lines and the source line. A solid state memory component can include a plurality of pillars located in a periphery portion of the solid state memory component, and memory cells adjacent to each of the pillars. Associated systems and methods are also disclosed.

公开(公告)号：US20180307412A1

公开(公告)日：2018-10-25

申请号：US15860540

申请日：2018-01-02

Applicant: Intel Corporation

Inventor： Jun Zhao ,  Gowrisankar Damarla ,  David A. Daycock ,  Gordon A. Haller ,  Sri Sai Sivakumar Vegunta ,  John B. Matovu ,  Matthew R. Park ,  Prakash Rau Mokhna Rau

IPC: G06F3/06 ,  H01L27/11582 ,  H01L27/11575 ,  H01L27/11573 ,  H01L27/11565

CPC classification number: G06F3/061 ,  G06F3/0655 ,  G06F3/0688 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582

Abstract: Solid state memory technology is disclosed. In one example, a solid state memory component can include a plurality of bit lines, a source line, and a plurality of non-functional memory pillars. Each non-functional memory pillar is electrically isolated from one or both of the plurality of bit lines and the source line. In another example, a solid state memory component can include a plurality of pillars located in a periphery portion of the solid state memory component, and memory cells adjacent to each of the pillars. Associated systems and methods are also disclosed.

公开(公告)号：US20190294330A1

公开(公告)日：2019-09-26

申请号：US16436917

申请日：2019-06-11

Applicant: Intel Corporation

Inventor： Jun Zhao ,  Gowrisankar Damarla ,  David A. Daycock ,  Gordon A. Haller ,  Sri Sai Sivakumar Vegunta ,  John B. Matovu ,  Matthew R. Park ,  Prakash Rau Mokhna Rau

IPC: G06F3/06 ,  H01L27/11582 ,  H01L27/11575 ,  H01L27/11573

Abstract: Solid state memory technology is disclosed. In one example, a solid state memory component can include a plurality of bit lines, a source line, and a plurality of non-functional memory pillars. Each non-functional memory pillar is electrically isolated from one or both of the plurality of bit lines and the source line. In another example, a solid state memory component can include a plurality of pillars located in a periphery portion of the solid state memory component, and memory cells adjacent to each of the pillars. Associated systems and methods are also disclosed.

公开(公告)号：US10318170B2

公开(公告)日：2019-06-11

申请号：US15860540

申请日：2018-01-02

Applicant: Intel Corporation

Inventor： Jun Zhao ,  Gowrisankar Damarla ,  David A. Daycock ,  Gordon A. Haller ,  Sri Sai Sivakumar Vegunta ,  John B. Matovu ,  Matthew R. Park ,  Prakash Rau Mokhna Rau

IPC: G11C16/06 ,  G06F3/06 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582 ,  H01L27/11565

Abstract: Solid state memory technology is disclosed. A solid state memory component can include a plurality of bit lines, a source line, and a plurality of non-functional memory pillars. Each non-functional memory pillar is electrically isolated from one or both of the plurality of bit lines and the source line. A solid state memory component can include a plurality of pillars located in a periphery portion of the solid state memory component, and memory cells adjacent to each of the pillars. Associated systems and methods are also disclosed.

公开(公告)号：US10096612B2

公开(公告)日：2018-10-09

申请号：US14853783

申请日：2015-09-14

Applicant: INTEL CORPORATION

Inventor： Sri Sai Sivakumar Vegunta ,  Gowrisankar Damarla ,  Jian Zhou

IPC: G06F12/00 ,  H01L27/11582 ,  H01L27/11573 ,  H01L21/3213 ,  H01L21/311 ,  H01L21/768 ,  G06F3/06 ,  H01L27/1157

Abstract: A three dimensional memory device is described having an array region and a periphery region. The array region has a three dimensional stack of storage cells. The periphery region has contacts that extend from above the three dimensional stack of storage cells to below the three dimensional stack of storage cells. The periphery region is substantially devoid of conducting and/or semi-conducting layers of the three dimensional stack of storage cells.