公开(公告)号：US20190033368A1

公开(公告)日：2019-01-31

申请号：US15801454

申请日：2017-11-02

Applicant: Intel Corporation

Inventor： Lakshminarayana Pappu ,  Robert P. Adler ,  Ki Yoon

IPC: G01R31/3187

Abstract: In one embodiment, an apparatus includes multiple die and at least one interconnect to couple the die. A first die includes one or more cores, a first fabric and a first fabric transactor coupled to the first fabric, the first fabric transactor to initiate a functional test of the apparatus in response to a test signal, cause at least one first test transaction to be sent to a second die, receive a first response to the at least one first test transaction from the second die, and identify, based at least in part on the first response to the at least one test transaction, a location of a failure and report the location of the failure to a destination. Other embodiments are described and claimed.

公开(公告)号：US20220131708A1

公开(公告)日：2022-04-28

申请号：US17546335

申请日：2021-12-09

Applicant: Intel Corporation

Inventor： Santosh Ghosh ,  Manoj Sastry ,  Ki Yoon

IPC: H04L9/32

Abstract: In one example an apparatus comprises verification circuitry to receive, in a RSA/ECDSA processor, an input message, compute, in the RSA/ECDSA processor, a hash digest (d) for the message, and provide the hash digest as an input to a XMSS/LMS processor. Other examples may be described.

公开(公告)号：US20220100873A1

公开(公告)日：2022-03-31

申请号：US17546290

申请日：2021-12-09

Applicant: Intel Corporation

Inventor： Ki Yoon ,  Georgina Saborio Dobles ,  Santosh Ghosh ,  Manoj Sastry

IPC: G06F21/60 ,  G06F21/64 ,  G06F21/57

Abstract: In one example an apparatus comprises signature circuitry to receive input variables comprising a value (X), a start index (i), a number of steps (s), a seed (SEED) and a memory address (ADRS) to store one or more context variables, and implement a loop for a multi-stage calculation of a Winternitz one-time signature (WOTS), wherein one or more WOTS hash functions are computed in each stage of the multi-stage calculation. Other examples may be described.

公开(公告)号：US11105854B2

公开(公告)日：2021-08-31

申请号：US15801454

申请日：2017-11-02

Applicant: Intel Corporation

Inventor： Lakshminarayana Pappu ,  Robert P. Adler ,  Ki Yoon

IPC: G01R31/3187 ,  G01R31/3185

Abstract: In one embodiment, an apparatus includes multiple die and at least one interconnect to couple the die. A first die includes one or more cores, a first fabric and a first fabric transactor coupled to the first fabric, the first fabric transactor to initiate a functional test of the apparatus in response to a test signal, cause at least one first test transaction to be sent to a second die, receive a first response to the at least one first test transaction from the second die, and identify, based at least in part on the first response to the at least one test transaction, a location of a failure and report the location of the failure to a destination. Other embodiments are described and claimed.

公开(公告)号：US09223668B2

公开(公告)日：2015-12-29

申请号：US13800185

申请日：2013-03-13

Applicant: INTEL CORPORATION

Inventor： Ki Yoon ,  Robert De Gruijl ,  Chai Ziv ,  Michael Klinglesmith

IPC: G06F11/00 ,  G06F11/26 ,  G06F11/273 ,  G06F11/36

CPC classification number: G06F11/26 ,  G06F11/2733 ,  G06F11/3636 ,  G06F11/3648

Abstract: A fabric trace hook is disclosed to enable debugging operations of agents operating in a peer-to-peer integrated on-chip system fabric. The fabric trace hook, embedded within the IOSF, includes programmable triggering and capturing logic, timestamp capability, and a security feature to disallow tracing of proprietary transactions. The fabric trace hook may operate in a lossy or lossless mode.

Abstract translation: 公开了一种织物跟踪钩，以便能够在对等集成片上系统结构中操作的代理的调试操作。 嵌入在IOSF中的结构跟踪钩子包括可编程触发和捕获逻辑，时间戳功能和安全功能，以禁止跟踪专有交易。 织物跟踪钩可以在有损或无损模式下操作。