公开(公告)号：US20190132198A1

公开(公告)日：2019-05-02

申请号：US16231807

申请日：2018-12-24

Applicant: INTEL CORPORATION

Inventor： Ang LI ,  Eng Hun OOI ,  Kuan Hua TAN

IPC: H04L12/24 ,  G06F12/02 ,  G06F9/50 ,  G06F9/30 ,  H04L29/06

Abstract: A handshake communication mechanism between a host and an end-point device permits multiple Base Address Registers (BAR registers) to be configured to size or resize the mapped address spaces associated with each BAR register. In one embodiment, the handshake communication mechanism includes a single address space reconfiguration request which may be transmitted in a single transaction layer packet, to request the configuration of multiple BAR registers of an end-point device. Other features and advantages may be realized, depending upon the particular application.

公开(公告)号：US20200278883A1

公开(公告)日：2020-09-03

申请号：US16878064

申请日：2020-05-19

Applicant: Intel Corporation

Inventor： Kuan Hua TAN ,  Sahar KHALILI ,  Eng Hun OOI ,  Shrinivas VENKATRAMAN ,  Dimpesh PATEL

IPC: G06F9/46 ,  G06F9/54 ,  G06F13/16 ,  G06F13/42 ,  G06F13/38 ,  G06F11/30

Abstract: A multilevel memory system includes a nonvolatile memory (NVM) device with an NVM media having a media write unit that is different in size than a host write unit of a host controller of the system that has the multilevel memory system. The memory device includes a media controller that controls writes to the NVM media. The host controller sends a write transaction to the media controller. The write transaction can include the write data in host write units, while the media controller will commit data in media write units to the NVM media. The media controller can send a transaction message to indicate whether the write data for the write transaction was successfully committed to the NVM media.