公开(公告)号：US20190132198A1

公开(公告)日：2019-05-02

申请号：US16231807

申请日：2018-12-24

Applicant: INTEL CORPORATION

Inventor： Ang LI ,  Eng Hun OOI ,  Kuan Hua TAN

IPC: H04L12/24 ,  G06F12/02 ,  G06F9/50 ,  G06F9/30 ,  H04L29/06

Abstract: A handshake communication mechanism between a host and an end-point device permits multiple Base Address Registers (BAR registers) to be configured to size or resize the mapped address spaces associated with each BAR register. In one embodiment, the handshake communication mechanism includes a single address space reconfiguration request which may be transmitted in a single transaction layer packet, to request the configuration of multiple BAR registers of an end-point device. Other features and advantages may be realized, depending upon the particular application.

公开(公告)号：US20200278883A1

公开(公告)日：2020-09-03

申请号：US16878064

申请日：2020-05-19

Applicant: Intel Corporation

Inventor： Kuan Hua TAN ,  Sahar KHALILI ,  Eng Hun OOI ,  Shrinivas VENKATRAMAN ,  Dimpesh PATEL

IPC: G06F9/46 ,  G06F9/54 ,  G06F13/16 ,  G06F13/42 ,  G06F13/38 ,  G06F11/30

Abstract: A multilevel memory system includes a nonvolatile memory (NVM) device with an NVM media having a media write unit that is different in size than a host write unit of a host controller of the system that has the multilevel memory system. The memory device includes a media controller that controls writes to the NVM media. The host controller sends a write transaction to the media controller. The write transaction can include the write data in host write units, while the media controller will commit data in media write units to the NVM media. The media controller can send a transaction message to indicate whether the write data for the write transaction was successfully committed to the NVM media.

公开(公告)号：US20230090431A1

公开(公告)日：2023-03-23

申请号：US17810845

申请日：2022-07-06

Applicant: Intel Corporation

Inventor： Elan BANIN ,  Eytan MANN ,  Rotem BANIN ,  Ronen GERNIZKY ,  Ofir DEGANI ,  Igal KUSHNIR ,  Shahar PORAT ,  Amir RUBIN ,  Vladimir VOLOKITIN ,  Elinor KASHANI ,  Dmitry FELSENSTEIN ,  Ayal ESHKOLI ,  Tal DAVIDSON ,  Eng Hun OOI ,  Yossi TSFATI ,  Ran SHIMON

IPC: H04B1/04 ,  H04L7/033

Abstract: An apparatus for generating a data signal comprises a processing circuit configured to generate the data signal, the data signal comprising a sequence of a first signal edge of a first type, a second signal edge of a second type, and a third signal edge of the first type, the first signal edge and the second signal edge being separated by a first time period corresponding to first data to be transmitted, and the second signal edge and the third signal edge being separated by a second time period corresponding to second data to be transmitted. An output interface circuit is configured to output the data signal.

公开(公告)号：US20160342328A1

公开(公告)日：2016-11-24

申请号：US14719234

申请日：2015-05-21

Applicant: INTEL CORPORATION

Inventor： Thanunathan RANGARAJAN ,  Eng Hun OOI ,  Madhusudhan RANGARAJAN ,  Robert W. CONE ,  Nishi AHUJA

IPC: G06F3/06 ,  G06F1/20

CPC classification number: G06F3/061 ,  G06F1/206 ,  G06F3/0625 ,  G06F3/0634 ,  G06F3/0653 ,  G06F3/0659 ,  G06F3/067 ,  G06F3/0689

Abstract: Provided are a computer readable storage media, method, and system for gathering sensed data from devices to manage host command transmission and cooling of the device. Host commands are retrieved from a host memory in a host to perform Input/Output operations with respect to a device. The retrieved host commands are transmitted to the device to perform the I/O operations of the host command. A monitor command is transmitted to obtain sensed data from the device while processing the host commands. A rate of transmitting the host commands is adjusted in response to determining that the sensed data received from the device in response to the monitor command satisfies a condition.

Abstract translation: 提供了一种用于从设备收集感测数据以管理主机命令传输和冷却设备的计算机可读存储介质，方法和系统。 从主机中的主机存储器检索主机命令，以对设备执行输入/输出操作。 检索到的主机命令被发送到设备以执行主机命令的I / O操作。 发送监视命令以在处理主机命令时从设备获得感测数据。 响应于确定响应于监视命令从设备接收到的感测数据满足条件，调整发送主机命令的速率。

公开(公告)号：US20180089137A1

公开(公告)日：2018-03-29

申请号：US15277893

申请日：2016-09-27

Applicant: INTEL CORPORATION

Inventor： Eng Hun OOI ,  Su Wei LIM

IPC: G06F13/42 ,  G06F11/10 ,  G06F11/34 ,  G06F11/30

CPC classification number: G06F13/4282 ,  G06F11/1004 ,  G06F11/3027 ,  G06F11/3037 ,  G06F11/3051 ,  G06F11/349 ,  G06F2213/0026

Abstract: An apparatus is described. The apparatus includes a point-to-point link interface circuit. The point-to-point link interface circuit is to support communication with a level of a multi-level system memory. The point-to-point link interface circuit includes a circuit to interlace payload data with cyclic redundancy check (CRC) values, where, different data segments of the payload are each appended with its own respective CRC value.

公开(公告)号：US20170213034A1

公开(公告)日：2017-07-27

申请号：US15419368

申请日：2017-01-30

Applicant: Intel Corporation

Inventor： Nitin V. SARANGDHAR ,  Robert J. ROYER, JR. ,  Eng Hun OOI ,  Brian R. MCFARLANE ,  Mukesh KATARIA

IPC: G06F21/57 ,  G06F12/14 ,  H04L29/06 ,  G06F9/44

CPC classification number: G06F21/572 ,  G06F9/4403 ,  G06F9/4406 ,  G06F9/4411 ,  G06F11/1417 ,  G06F21/57 ,  G06F21/575 ,  G06F2212/1052 ,  G06F2221/03 ,  G06F2221/033

Abstract: A hardware platform includes a nonvolatile storage device that can store system firmware as well as code for the primary operating system for the hardware platform. The hardware platform includes a controller that determines the hardware platform lacks functional firmware to boot the primary operating system from the storage device. The controller accesses a firmware image from an external interface that interfaces a device external to the hardware platform, where the external device is a firmware image source. The controller provisions the firmware from the external device to the storage device and initiates a boot sequence from the provisioned firmware.