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Patent Agency Ranking
公开(公告)号：US12107557B2
公开(公告)日：2024-10-01
申请号：US17426065
申请日：2019-10-10
Applicant: INTEL CORPORATION
Inventor： Daniel Gruber , Michael Kalcher
CPC classification number: H03F3/505 , G05F1/575 , G05F1/618 , H03F3/45636
Abstract: Examples relate to a buffered flipped voltage follower circuit arrangement, low dropout voltage regulators, a capacitive digital-to-analog converter, a transceiver for wireless communication, a mobile communication device, a base station transceiver, and to a method for forming a buffered flipped voltage follower circuit arrangement. The buffered flipped voltage follower circuit arrangement comprises a first transistor (Mp) comprising a first terminal, a second terminal and a gate terminal. The buffered flipped voltage follower circuit arrangement comprises a second transistor (Mc) comprising a first terminal, a second terminal and a gate terminal. The buffered flipped voltage follower circuit arrangement comprises a buffer circuit comprising an input terminal and an output terminal. The buffered flipped voltage follower circuit arrangement a feed-forward compensation circuit (−gmf) comprising an input terminal and an output terminal. The first terminal of the first transistor (Mp) is coupled to a supply voltage of the flipped voltage follower circuit. The second terminal of the first transistor (Mp) is coupled with the first terminal of the second transistor (Mc) and with an output voltage terminal of the buffered flipped voltage follower circuit arrangement. The second terminal of the second transistor (Mc) is coupled with the input terminal of the buffer circuit and with the output terminal of the feed-forward compensation circuit (−gmf). The gate terminal of the first transistor (MP) is coupled with the output terminal of the buffer circuit and with the input terminal of the feed-forward compensation circuit (−gmf).
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公开(公告)号：US12034452B2
公开(公告)日：2024-07-09
申请号：US17132000
申请日：2020-12-23
Applicant: Intel Corporation
Inventor： Daniel Gruber , Michael Kalcher , Martin Clara
Abstract: A Digital-to-Analog Converter (DAC) is provided. The DAC includes a code converter circuit configured to sequentially receive first digital control codes for controlling N digital-to-analog converter cells. N is an integer greater than one. The code converter circuit is further configured to convert the first digital control codes to second digital control codes. Additionally, the DAC includes a bit-shifter circuit configured to receive shift codes for the second digital control codes. The shift codes are obtained using dynamic element matching and indicate a respective circular shift by ri bit positions for the i-th second digital control code, wherein ri is an integer smaller than N−1. The bit-shifter circuit is further configured to generate third digital control codes by circularly shifting the second digital codes based on the shift codes. In addition, the DAC includes a cell activation circuit configured to selectively activate one or more of the N digital-to-analog converter cells based on the third digital control codes.
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公开(公告)号：US10965308B1
公开(公告)日：2021-03-30
申请号：US16912792
申请日：2020-06-26
Applicant: Intel Corporation
Inventor： Daniel Gruber , Martin Clara , Michael Kalcher
Abstract: A digital-to-analog converter comprises a plurality of first digital-to-analog converter cells configured to generate a first analog signal based on first digital data, wherein the first digital-to-analog converter cells of the plurality of first digital-to-analog converter cells are coupled to a first output node for coupling to a first load. Further, the digital-to-analog converter comprises a plurality of second digital-to-analog converter cells configured to generate one or more second analog signals based on second digital data, wherein the second digital-to-analog converter cells of the plurality of second digital-to-analog converter cells are coupled to one or more second output nodes, and wherein the plurality of first digital-to-analog converter cells and the plurality of second digital-to-analog converter cells are coupled to a power supply node for coupling to a mutual power supply.
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4.发明授权公开(公告)号：US12261622B2
公开(公告)日：2025-03-25
申请号：US17358152
申请日：2021-06-25
Applicant: Intel Corporation
Inventor： Michael Kalcher , Daniel Gruber , Martin Clara
Abstract: Circuitry for digital-to-analog conversion is provided. The circuitry includes a driver circuit and a weighting resistor circuit coupled to an output of the driver circuit. The weighting resistor circuit includes a first resistive sub-circuit coupled to the output of the driver circuit and an intermediate node. The weighting resistor further includes a second resistive sub-circuit coupled to the intermediate node and a common node. Further, the weighting circuit includes a third resistive sub-circuit coupled to the intermediate node and an output of the circuitry. The resistivity of the second resistive sub-circuit is equal to or smaller than the resistivity of the first resistive sub-circuit.
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公开(公告)号：US10651869B1
公开(公告)日：2020-05-12
申请号：US16364891
申请日：2019-03-26
Applicant: Intel IP Corporation , Intel Corporation
Inventor： Davide Ponton , Michael Kalcher , Alan Paussa , Edwin Thaller , Franz Kuttner , Daniel Gruber
Abstract: A radio frequency digital-to-analog converter (RFDAC) circuit includes an RFDAC array circuit including an array of cells arranged into a plurality of segments. Each segment of the plurality of segments is configured to process input data signals. The RFDAC array circuit is configured to process an input data based on activating a set of segments of the plurality of segments, forming a set of active segments, and when the sign of the input data is changed, deactivate a partially active segment of the set of active segments and activate a sign change segment within the RFDAC array circuit. The sign change segment includes a segment within the plurality of segments of the RFDAC array circuit that is different from the set of active segments.
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