公开(公告)号：US11354135B2

公开(公告)日：2022-06-07

申请号：US16648770

申请日：2017-12-25

Applicant: INTEL CORPORATION

Inventor： Zhiqiang Qin ,  Tao Xu ,  Qing Huang

IPC: G06F9/44 ,  G06F12/08 ,  G06F9/4401 ,  G06F12/0871

Abstract: A computing device that implements a multithread parallel processing computing platform prior to initialization of system memory is provided. To implement this platform, the computing device executes enhanced firmware that defines a plurality of application processors (APs) under the control of a boot-strap processor (BSP). The BSP preserves backward compatibility of the APs by configuring cross-reference circuitry (e.g., a programmable attribute map) to reroute memory access requests generated by the APs that are addressed to a wakeup buffer to a redirected memory address. Memory at the redirected memory address stores AP initialization instructions and instructions to retrieve and process early stage process instructions stored elsewhere (e.g., in fast access cache memory). The APs, in parallel, execute the initialization instructions and the early stage process instructions stored in cache to complete an early stage process, such as memory training.

公开(公告)号：US11080135B2

公开(公告)日：2021-08-03

申请号：US16617411

申请日：2017-06-27

Applicant: Intel Corporation

Inventor： Yingwen Chen ,  Anil Agrawal ,  Fang Yuan ,  Qing Huang

IPC: G06F11/10 ,  G01R31/317

Abstract: An example apparatus to monitor memory includes an error manager to compare a first memory location of a first error in the memory to a plurality of memory locations in an error history log, the plurality of memory locations previously identified in the error history log based on errors detected in the memory locations, ones of the memory locations associated with corresponding counters that track the errors detected in the memory locations, and update a first one of the counters corresponding to the first memory location when a first address of the first memory location matches a second address of one of the memory locations in the error history log. The example apparatus further includes a command generator to transmit a command to an error corrector to perform error correction on the first memory location when the first one of the counters satisfies a threshold.

公开(公告)号：US20200249957A1

公开(公告)日：2020-08-06

申请号：US16648770

申请日：2017-12-25

Applicant: INTEL CORPORATION

Inventor： Zhiqiang Qin ,  Tao Xu ,  Qing Huang

IPC: G06F9/4401 ,  G06F12/0871

Abstract: A computing device that implements a multithread parallel processing computing platform prior to initialization of system memory is provided. To implement this platform, the computing device executes enhanced firmware that defines a plurality of application processors (APs) under the control of a boot-strap processor (BSP). The BSP preserves backward compatibility of the APs by configuring cross-reference circuitry (e.g., a programmable attribute map) to reroute memory access requests generated by the APs that are addressed to a wakeup buffer to a redirected memory address. Memory at the redirected memory address stores AP initialization instructions and instructions to retrieve and process early stage process instructions stored elsewhere (e.g., in fast access cache memory). The APs, in parallel, execute the initialization instructions and the early stage process instructions stored in cache to complete an early stage process, such as memory training.

公开(公告)号：US20200151056A1

公开(公告)日：2020-05-14

申请号：US16617411

申请日：2017-06-27

Applicant: Intel Corporation

Inventor： Yingwen Chen ,  Anil Agrawal ,  Fang Yuan ,  Qing Huang

IPC: G06F11/10 ,  G01R31/317

Abstract: An example apparatus to monitor memory includes an error manager to compare a first memory location of a first error in the memory to a plurality of memory locations in an error history log, the plurality of memory locations previously identified in the error history log based on errors detected in the memory locations, ones of the memory locations associated with corresponding counters that track the errors detected in the memory locations, and update a first one of the counters corresponding to the first memory location when a first address of the first memory location matches a second address of one of the memory locations in the error history log. The example apparatus further includes a command generator to transmit a command to an error corrector to perform error correction on the first memory location when the first one of the counters satisfies a threshold.