公开(公告)号：US11354135B2

公开(公告)日：2022-06-07

申请号：US16648770

申请日：2017-12-25

Applicant: INTEL CORPORATION

Inventor： Zhiqiang Qin ,  Tao Xu ,  Qing Huang

IPC: G06F9/44 ,  G06F12/08 ,  G06F9/4401 ,  G06F12/0871

Abstract: A computing device that implements a multithread parallel processing computing platform prior to initialization of system memory is provided. To implement this platform, the computing device executes enhanced firmware that defines a plurality of application processors (APs) under the control of a boot-strap processor (BSP). The BSP preserves backward compatibility of the APs by configuring cross-reference circuitry (e.g., a programmable attribute map) to reroute memory access requests generated by the APs that are addressed to a wakeup buffer to a redirected memory address. Memory at the redirected memory address stores AP initialization instructions and instructions to retrieve and process early stage process instructions stored elsewhere (e.g., in fast access cache memory). The APs, in parallel, execute the initialization instructions and the early stage process instructions stored in cache to complete an early stage process, such as memory training.

公开(公告)号：US20200249957A1

公开(公告)日：2020-08-06

申请号：US16648770

申请日：2017-12-25

Applicant: INTEL CORPORATION

Inventor： Zhiqiang Qin ,  Tao Xu ,  Qing Huang

IPC: G06F9/4401 ,  G06F12/0871

Abstract: A computing device that implements a multithread parallel processing computing platform prior to initialization of system memory is provided. To implement this platform, the computing device executes enhanced firmware that defines a plurality of application processors (APs) under the control of a boot-strap processor (BSP). The BSP preserves backward compatibility of the APs by configuring cross-reference circuitry (e.g., a programmable attribute map) to reroute memory access requests generated by the APs that are addressed to a wakeup buffer to a redirected memory address. Memory at the redirected memory address stores AP initialization instructions and instructions to retrieve and process early stage process instructions stored elsewhere (e.g., in fast access cache memory). The APs, in parallel, execute the initialization instructions and the early stage process instructions stored in cache to complete an early stage process, such as memory training.

公开(公告)号：US11782645B2

公开(公告)日：2023-10-10

申请号：US17568956

申请日：2022-01-05

Applicant: INTEL CORPORATION

Inventor： Zhi Yong Chen ,  Zhiqiang Qin ,  Xueyan Wang ,  Fang Yuan

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0631 ,  G06F3/0673

Abstract: Logic may store data structures for two or more processors in memory such as cache, system management memory, protected memory, or other memory. Logic may compress the data structures to be stored in the memory. Logic may determine a reference data structure, store the reference data structure in the memory, determine a difference between a data structure for a second processor and the reference data structure, and store the difference in the memory. Logic may store the difference in the memory within a data structure such as a linked list or a bitmap. Logic may decompress the difference by combining the difference with the reference data structure. Logic may expand the useable data region to include cache in the two or more processors. Logic may instruct two or more processors to store their processor data structures in their respective caches and perform initialization with the processor data structures.

公开(公告)号：US11288010B2

公开(公告)日：2022-03-29

申请号：US16638694

申请日：2017-09-25

Applicant: INTEL CORPORATION

Inventor： Zhi Yong Chen ,  Zhiqiang Qin ,  Xueyan Wang ,  Fang Yuan

IPC: G06F3/06

Abstract: Logic may store data structures for two or more processors in memory such as cache, system management memory, protected memory, or other memory. Logic may compress the data structures to be stored in the memory. Logic may determine a reference data structure, store the reference data structure in the memory, determine a difference between a data structure for a second processor and the reference data structure, and store the difference in the memory. Logic may store the difference in the memory within a data structure such as a linked list or a bitmap. Logic may decompress the difference by combining the difference with the reference data structure. Logic may expand the useable data region to include cache in the two or more processors. Logic may instruct two or more processors to store their processor data structures in their respective caches and perform initialization with the processor data structures.

公开(公告)号：US10831216B2

公开(公告)日：2020-11-10

申请号：US15573313

申请日：2016-12-22

Applicant: INTEL CORPORATION

Inventor： Ke Han ,  Zhen Zhou ,  Guangyu Ren ,  Zhiqiang Qin

IPC: G05D1/10 ,  B64C39/02 ,  G01C5/06 ,  G01S5/02 ,  G01S5/06 ,  G01S11/06 ,  G01S19/46

Abstract: Apparatus, method and storage medium associated with UAV position estimation are disclosed herein. In embodiments, an UAV may comprise a transmitter-receiver arrangement to transmit and receive communication signals, including receipt of absolute positioning system (APS) signals from one or more APS sensors, and wireless signals from one or more proximately located other UAVs; one or more motors or engines to provide propulsive force for the UAV; and a flight controller coupled to the transmitter-receiver arrangement and the one or more motors or engines to control at least the one or more motors or engines to provide propulsive force to navigate the UAV, based at least in part on the APS and relative positioning signals. Other embodiments may be disclosed or claimed.