公开(公告)号：US11327918B2

公开(公告)日：2022-05-10

申请号：US17041519

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Zhi Yong Chen ,  Sarathy Jayakumar ,  Yi Zeng ,  Wenjuan Mao ,  Anil Agrawal

IPC: G06F13/40 ,  G06F9/4401 ,  G06F11/20

Abstract: There is disclosed in one example a multi-core computing system configured to provide a hot-swappable CPU0, including: a first CPU in a first CPU socket and a second CPU in a second CPU socket; a switch including a first media interface to the first CPU socket and a second media interface to the second CPU socket; and one or more mediums including non-transitory instructions to detect a hot swap event of the first CPU, designate the second CPU as CPU0, determine that a new CPU has replaced the first CPU, operate the switch to communicatively couple the new CPU to a backup initialization code store via the first media interface, initialize the new CPU, and designate the new CPU as CPUN, wherein N≠0.

公开(公告)号：US11080135B2

公开(公告)日：2021-08-03

申请号：US16617411

申请日：2017-06-27

Applicant: Intel Corporation

Inventor： Yingwen Chen ,  Anil Agrawal ,  Fang Yuan ,  Qing Huang

IPC: G06F11/10 ,  G01R31/317

Abstract: An example apparatus to monitor memory includes an error manager to compare a first memory location of a first error in the memory to a plurality of memory locations in an error history log, the plurality of memory locations previously identified in the error history log based on errors detected in the memory locations, ones of the memory locations associated with corresponding counters that track the errors detected in the memory locations, and update a first one of the counters corresponding to the first memory location when a first address of the first memory location matches a second address of one of the memory locations in the error history log. The example apparatus further includes a command generator to transmit a command to an error corrector to perform error correction on the first memory location when the first one of the counters satisfies a threshold.

公开(公告)号：US20210209052A1

公开(公告)日：2021-07-08

申请号：US17041519

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Zhi Yong Chen ,  Sarathy Jayakumar ,  Yi Zeng ,  Wenjuan Mao ,  Anil Agrawal

IPC: G06F13/40 ,  G06F9/4401

Abstract: There is disclosed in one example a multi-core computing system configured to provide a hot-swappable CPU0, including: a first CPU in a first CPU socket and a second CPU in a second CPU socket; a switch including a first media interface to the first CPU socket and a second media interface to the second CPU socket; and one or more mediums including non-transitory instructions to detect a hot swap event of the first CPU, designate the second CPU as CPU0, determine that a new CPU has replaced the first CPU, operate the switch to communicatively couple the new CPU to a backup initialization code store via the first media interface, initialize the new CPU, and designate the new CPU as CPUN, wherein N≠0.

公开(公告)号：US20160004587A1

公开(公告)日：2016-01-07

申请号：US14428338

申请日：2014-04-16

Applicant: INTEL CORPORATION

Inventor： Anil Agrawal ,  Satish Muthiyalu ,  Yingwen Chen ,  Meera Ganesan

IPC: G06F11/07 ,  G06F3/06

CPC classification number: G06F11/0793 ,  G06F3/0614 ,  G06F3/0652 ,  G06F3/0673 ,  G06F11/073 ,  G06F11/0751 ,  G06F11/079 ,  G06F11/106 ,  G11C29/52 ,  G11C2029/0409

Abstract: Techniques and mechanisms for providing error detection and correction for a platform comprising a memory including one or more spare memory segments. In an embodiment, a memory controller performs first scrubbing operations including detection for errors in a plurality of currently active memory segments. Additional patrol scrubbing is performed for one or more memory segments while the memory segments are each available for activation as a replacement memory segment. In another embodiment, a first handler process (but not a second handler process) is signaled if an uncorrectable error event is detected based on the active segment scrubbing, whereas the second handler process (but not the first handler process) is signaled if an uncorrectable error event is detected based on the spare segment scrubbing. Of the first handler process and the second handler process, only signaling of the first handler process results in a crash event of the platform.

Abstract translation: 用于为包括一个或多个备用存储器段的存储器的平台提供错误检测和校正的技术和机制。 在一个实施例中，存储器控制器执行包括对多个当前活动存储器段中的错误的检测的第一擦除操作。 对一个或多个存储器段执行附加的巡检擦除，同时存储器段可用作激活作为替换存储器段。 在另一个实施例中，如果基于活动段擦除检测到不可校正的错误事件，则发信号通知第一处理程序进程（但不是第二处理程序进程），而如果不可校正的第二处理程序进程（但不是第一处理程序进程） 基于备用段擦除检测错误事件。 在第一个处理程序进程和第二个处理程序进程中，只有第一个处理程序进程的信号会导致平台的崩溃事件。

公开(公告)号：US20210311818A1

公开(公告)日：2021-10-07

申请号：US17255109

申请日：2018-12-11

Applicant: INTEL CORPORATION

Inventor： Vincent Zimmer ,  Anil Agrawal ,  Dujian Wu ,  Shijian Ge ,  Zhenglong Wu

IPC: G06F11/07

Abstract: Systems, apparatuses and methods may provide for technology that handles failures in memory hardware (e.g., dynamic random access memory (DRAM)) via runtime post package repair. Such technology may include operations to perform a runtime post package repair in response to a memory hardware failure detected in the memory. In such an example, the runtime post package repair may be done after power up boot operations have been completed.

公开(公告)号：US20200151056A1

公开(公告)日：2020-05-14

申请号：US16617411

申请日：2017-06-27

Applicant: Intel Corporation

Inventor： Yingwen Chen ,  Anil Agrawal ,  Fang Yuan ,  Qing Huang

IPC: G06F11/10 ,  G01R31/317

Abstract: An example apparatus to monitor memory includes an error manager to compare a first memory location of a first error in the memory to a plurality of memory locations in an error history log, the plurality of memory locations previously identified in the error history log based on errors detected in the memory locations, ones of the memory locations associated with corresponding counters that track the errors detected in the memory locations, and update a first one of the counters corresponding to the first memory location when a first address of the first memory location matches a second address of one of the memory locations in the error history log. The example apparatus further includes a command generator to transmit a command to an error corrector to perform error correction on the first memory location when the first one of the counters satisfies a threshold.

公开(公告)号：US09535782B2

公开(公告)日：2017-01-03

申请号：US14428338

申请日：2014-04-16

Applicant: Intel Corporation

Inventor： Anil Agrawal ,  Satish Muthiyalu ,  Yingwen Chen ,  Meera Ganesan

IPC: G06F11/00 ,  G06F11/07 ,  G11C29/52 ,  G06F3/06 ,  G11C29/04

CPC classification number: G06F11/0793 ,  G06F3/0614 ,  G06F3/0652 ,  G06F3/0673 ,  G06F11/073 ,  G06F11/0751 ,  G06F11/079 ,  G06F11/106 ,  G11C29/52 ,  G11C2029/0409

Abstract: Techniques and mechanisms for providing error detection and correction for a platform comprising a memory including one or more spare memory segments. In an embodiment, a memory controller performs first scrubbing operations including detection for errors in a plurality of currently active memory segments. Additional patrol scrubbing is performed for one or more memory segments while the memory segments are each available for activation as a replacement memory segment. In another embodiment, a first handler process (but not a second handler process) is signaled if an uncorrectable error event is detected based on the active segment scrubbing, whereas the second handler process (but not the first handler process) is signaled if an uncorrectable error event is detected based on the spare segment scrubbing. Of the first handler process and the second handler process, only signaling of the first handler process results in a crash event of the platform.

Abstract translation: 用于为包括一个或多个备用存储器段的存储器的平台提供错误检测和校正的技术和机制。 在一个实施例中，存储器控制器执行包括对多个当前活动存储器段中的错误的检测的第一擦除操作。 对一个或多个存储器段执行附加的巡检擦除，同时存储器段可用作激活作为替换存储器段。 在另一个实施例中，如果基于活动段擦除检测到不可校正的错误事件，则发信号通知第一处理程序进程（但不是第二处理程序进程），而如果不可校正的第二处理程序进程（但不是第一处理程序进程） 基于备用段擦除检测错误事件。 在第一个处理程序进程和第二个处理程序进程中，只有第一个处理程序进程的信号会导致平台的崩溃事件。