公开(公告)号：US20180267844A1

公开(公告)日：2018-09-20

申请号：US15537357

申请日：2015-11-24

Applicant: Intel Corporation

Inventor： BRIAN T. LEWIS ,  RAJKISHORE BARIK ,  TATIANA SHPEISMAN

IPC: G06F9/54 ,  G06T1/20

CPC classification number: G06F9/544 ,  G06T1/20

Abstract: Generally, this disclosure provides systems, devices, methods and computer readable media for implementing function callback requests between a first processor (e.g., a GPU) and a second processor (e.g., a CPU). The system may include a shared virtual memory (SVM) coupled to the first and second processors, the SVM configured to store at least one double-ended queue (Deque). An execution unit (EU) of the first processor may be associated with a first of the Deques and configured to push the callback requests to that first Deque. A request handler thread executing on the second processor may be configured to: pop one of the callback requests from the first Deque; execute a function specified by the popped callback request; and generate a completion signal to the EU in response to completion of the function.

公开(公告)号：US20190258533A1

公开(公告)日：2019-08-22

申请号：US16282553

申请日：2019-02-22

Applicant: INTEL CORPORATION

Inventor： BRIAN T. LEWIS ,  RAJKISHORE BARIK ,  TATIANA SHPEISMAN

IPC: G06F9/54 ,  G06T1/20

Abstract: Generally, this disclosure provides systems, devices, methods and computer readable media for implementing function callback requests between a first processor (e.g., a GPU) and a second processor (e.g., a CPU). The system may include a shared virtual memory (SVM) coupled to the first and second processors, the SVM configured to store at least one double-ended queue (Deque). An execution unit (EU) of the first processor may be associated with a first of the Deques and configured to push the callback requests to that first Deque. A request handler thread executing on the second processor may be configured to: pop one of the callback requests from the first Deque; execute a function specified by the popped callback request; and generate a completion signal to the EU in response to completion of the function.

公开(公告)号：US20160055612A1

公开(公告)日：2016-02-25

申请号：US14583247

申请日：2014-12-26

Applicant: Intel Corporation

Inventor： RAJKISHORE BARIK ,  Tatiana Shpeisman ,  Brian T. Lewis ,  Rashid Kaleem

IPC: G06T1/20 ,  G09G5/00

CPC classification number: G06T1/20 ,  G06F3/14 ,  G09G5/001 ,  G09G5/363 ,  G09G2360/08

Abstract: Generally, this disclosure provides systems, devices, methods and computer readable media for adaptive scheduling of task assignment among heterogeneous processor cores. The system may include any number of CPUs, a graphics processing unit (GPU) and memory configured to store a pool of work items to be shared by the CPUs and GPU. The system may also include a GPU proxy profiling module associated with one of the CPUs to profile execution of a first portion of the work items on the GPU. The system may further include profiling modules, each associated with one of the CPUs, to profile execution of a second portion of the work items on each of the CPUs. The measured profiling information from the CPU profiling modules and the GPU proxy profiling module is used to calculate a distribution ratio for execution of a remaining portion of the work items between the CPUs and the GPU.

Abstract translation: 通常，本公开提供了用于在异构处理器核之间的任务分配的自适应调度的系统，设备，方法和计算机可读介质。 该系统可以包括任何数量的CPU，图形处理单元（GPU）和被配置为存储要被CPU和GPU共享的工作项池的存储器。 该系统还可以包括与CPU之一相关联的GPU代理分析模块，以对GPU上的工作项的第一部分的执行进行分析。 该系统可以进一步包括分析模块，每个与每个CPU之一相关联的分析模块，以描绘每个CPU上的工作项的第二部分的执行。 来自CPU分析模块和GPU代理分析模块的测量分析信息用于计算用于执行CPU和GPU之间的工作项目的剩余部分的分配比率。