公开(公告)号：US20230315481A1

公开(公告)日：2023-10-05

申请号：US18312079

申请日：2023-05-04

Applicant: Intel Corporation

Inventor： ELMOUSTAPHA OULD-AHMED-VALL ,  BARATH LAKSHMANAN ,  TATIANA SHPEISMAN ,  Joydeep Ray ,  Ping T. Tang ,  Michael Strickland ,  Xiaoming Chen ,  Anbang Yao ,  Ben J. Ashbaugh ,  Linda L. Hurd ,  Liwei Ma

IPC: G06F9/38 ,  G06F9/30 ,  G06F13/42 ,  G06F13/40 ,  G06N20/00 ,  G06T1/20 ,  G06N3/063 ,  G06N3/084 ,  G06N20/10 ,  G06N3/044 ,  G06N3/045 ,  G06F9/50 ,  G06F15/80 ,  G06N3/00

CPC classification number: G06F9/3887 ,  G06F9/3001 ,  G06F9/30014 ,  G06F9/30036 ,  G06F9/30094 ,  G06F9/30109 ,  G06F9/30112 ,  G06F9/3016 ,  G06F9/3851 ,  G06F9/3891 ,  G06F9/50 ,  G06F13/4068 ,  G06F13/4282 ,  G06F15/80 ,  G06N3/00 ,  G06N3/044 ,  G06N3/045 ,  G06N3/063 ,  G06N3/084 ,  G06N20/00 ,  G06N20/10 ,  G06T1/20 ,  G06F2213/0026

Abstract: Described herein is a general-purpose graphics processing unit including a multiprocessor having a single instruction, multiple thread, SIMT, architecture. The multiprocessor comprises multiple sets of compute units each having a first logic unit configured to perform floating-point operations and a second logic unit configured to perform integer operations, with a thread of the floating-point instruction being executed in parallel with a thread of the integer instruction.

公开(公告)号：US20220382555A1

公开(公告)日：2022-12-01

申请号：US17839856

申请日：2022-06-14

Applicant: Intel Corporation

Inventor： ELMOUSTAPHA OULD-AHMED-VALL ,  BARATH LAKSHMANAN ,  TATIANA SHPEISMAN ,  Joydeep Ray ,  Ping T. Tang ,  Michael Strickland ,  Xiaoming Chen ,  Anbang Yao ,  Ben J. Ashbaugh ,  Linda L. Hurd ,  Liwei Ma

IPC: G06F9/38 ,  G06F9/30 ,  G06F13/42 ,  G06F13/40 ,  G06N20/00 ,  G06T1/20 ,  G06N3/04 ,  G06N3/063 ,  G06N3/08 ,  G06N20/10 ,  G06F9/50 ,  G06F15/80 ,  G06N3/00

Abstract: One embodiment provides for a graphics processing unit (GPU) to accelerate machine learning operations, the GPU comprising an instruction cache to store a first instruction and a second instruction, the first instruction to cause the GPU to perform a floating-point operation, including a multi-dimensional floating-point operation, and the second instruction to cause the GPU to perform an integer operation; and a general-purpose graphics compute unit having a single instruction, multiple thread architecture, the general-purpose graphics compute unit to concurrently execute the first instruction and the second instruction.

公开(公告)号：US20190332869A1

公开(公告)日：2019-10-31

申请号：US16379176

申请日：2019-04-09

Applicant: Intel Corporation

Inventor： MAYURESH M. VARERKAR ,  BARNAN DAS ,  NARAYAN BISWAL ,  STANLEY J. BARAN ,  GOKCEN CILINGIR ,  NILESH V. SHAH ,  ARCHIE SHARMA ,  SHERINE ABDELHAK ,  SACHIN GODSE ,  FARSHAD AKHBARI ,  NARAYAN SRINIVASA ,  ALTUG KOKER ,  NADATHUR RAJAGOPALAN SATISH ,  DUKHWAN KIM ,  FENG CHEN ,  ABHISHEK R. APPU ,  JOYDEEP RAY ,  PING T. TANG ,  MICHAEL S. STRICKLAND ,  XIAOMING CHEN ,  ANBANG YAO ,  TATIANA SHPEISMAN ,  VASANTH RANGANATHAN ,  SANJEEV JAHAGIRDAR

IPC: G06K9/00 ,  G06N3/063 ,  G06T1/20 ,  G06N3/08 ,  G06N3/04

Abstract: A mechanism is described for facilitating person tracking and data security in machine learning at autonomous machines. A method of embodiments, as described herein, includes detecting, by a camera associated with one or more trackers, a person within a physical vicinity, where detecting includes capturing one or more images the person. The method may further include tracking, by the one or more trackers, the person based on the one or more images of the person, where tracking includes collect tracking data relating to the person. The method may further include selecting a tracker of the one or more trackers as a preferred tracker based on the tracking data.

公开(公告)号：US20190258533A1

公开(公告)日：2019-08-22

申请号：US16282553

申请日：2019-02-22

Applicant: INTEL CORPORATION

Inventor： BRIAN T. LEWIS ,  RAJKISHORE BARIK ,  TATIANA SHPEISMAN

IPC: G06F9/54 ,  G06T1/20

Abstract: Generally, this disclosure provides systems, devices, methods and computer readable media for implementing function callback requests between a first processor (e.g., a GPU) and a second processor (e.g., a CPU). The system may include a shared virtual memory (SVM) coupled to the first and second processors, the SVM configured to store at least one double-ended queue (Deque). An execution unit (EU) of the first processor may be associated with a first of the Deques and configured to push the callback requests to that first Deque. A request handler thread executing on the second processor may be configured to: pop one of the callback requests from the first Deque; execute a function specified by the popped callback request; and generate a completion signal to the EU in response to completion of the function.

公开(公告)号：US20180307494A1

公开(公告)日：2018-10-25

申请号：US15494773

申请日：2017-04-24

Applicant: Intel Corporation

Inventor： ELMOUSTAPHA OULD-AHMED-VALL ,  BARATH LAKSHMANAN ,  TATIANA SHPEISMAN ,  Joydeep Ray ,  Ping T. Tang ,  Michael Strickland ,  Xiaoming Chen ,  Anbang Yao ,  Ben J. Ashbaugh ,  Linda L. Hurd ,  Liwei Ma

IPC: G06F9/38 ,  G06F9/30 ,  G06F13/42 ,  G06F13/40 ,  G06N99/00

CPC classification number: G06F9/3887 ,  G06F1/32 ,  G06F9/3001 ,  G06F9/30014 ,  G06F9/30036 ,  G06F9/30094 ,  G06F9/30109 ,  G06F9/30112 ,  G06F9/3016 ,  G06F9/3851 ,  G06F9/3891 ,  G06F9/50 ,  G06F13/4068 ,  G06F13/4282 ,  G06F15/80 ,  G06F2213/0026 ,  G06N3/00 ,  G06N3/0445 ,  G06N3/0454 ,  G06N3/063 ,  G06N3/084 ,  G06N20/00 ,  G06T1/20

Abstract: One embodiment provides for a compute apparatus to perform machine learning operations, the compute apparatus comprising instruction decode logic to decode a single instruction including multiple operands into a single decoded instruction, the multiple operands having differing precisions and a general-purpose graphics compute unit including a first logic unit and a second logic unit, the general-purpose graphics compute unit to execute the single decoded instruction, wherein to execute the single decoded instruction includes to perform a first instruction operation on a first set of operands of the multiple operands at a first precision and a simultaneously perform second instruction operation on a second set of operands of the multiple operands at a second precision.

公开(公告)号：US20190146800A1

公开(公告)日：2019-05-16

申请号：US16227645

申请日：2018-12-20

Applicant: Intel Corporation

Inventor： ELMOUSTAPHA OULD-AHMED-VALL ,  BARATH LAKSHMANAN ,  TATIANA SHPEISMAN ,  Joydeep Ray ,  Ping T. Tang ,  Michael Strickland ,  Xiaoming Chen ,  Anbang Yao ,  Ben J. Ashbaugh ,  Linda L. Hurd ,  Liwei Ma

IPC: G06F9/38 ,  G06N20/00 ,  G06F15/80 ,  G06F13/42 ,  G06F9/30 ,  G06F13/40 ,  G06T1/20 ,  G06N3/00 ,  G06F9/50

Abstract: One embodiment provides for a general-purpose graphics processing unit comprising a streaming multiprocessor having a single instruction, multiple thread (SIMT) architecture including hardware multithreading. The streaming multiprocessor comprises multiple processing blocks including multiple processing cores. The processing cores include independent integer and floating-point data paths that are configurable to concurrently execute multiple independent instructions. A memory is coupled with the multiple processing blocks.

公开(公告)号：US20180307495A1

公开(公告)日：2018-10-25

申请号：US15819167

申请日：2017-11-21

Applicant: Intel Corporation

Inventor： ELMOUSTAPHA OULD-AHMED-VALL ,  BARATH LAKSHMANAN ,  TATIANA SHPEISMAN ,  Joydeep Ray ,  Ping T. Tang ,  Michael Strickland ,  Xiaoming Chen ,  Anbang Yao ,  Ben J. Ashbaugh ,  Linda L. Hurd ,  Liwei Ma

IPC: G06F9/38 ,  G06N99/00 ,  G06F13/40 ,  G06F13/42 ,  G06F9/30

CPC classification number: G06F9/3887 ,  G06F9/3001 ,  G06F9/30014 ,  G06F9/30036 ,  G06F9/30094 ,  G06F9/30109 ,  G06F9/30112 ,  G06F9/3016 ,  G06F9/3802 ,  G06F9/3836 ,  G06F9/3851 ,  G06F9/50 ,  G06F13/4068 ,  G06F13/4282 ,  G06F15/80 ,  G06F2213/0026 ,  G06N3/00 ,  G06N99/005 ,  G06T1/20

Abstract: One embodiment provides for a graphics processing unit (GPU) to accelerate machine learning operations, the GPU comprising an instruction cache to store a first instruction and a second instruction, the first instruction to cause the GPU to perform a floating-point operation, including a multi-dimensional floating-point operation, and the second instruction to cause the GPU to perform an integer operation; and a general-purpose graphics compute unit having a single instruction, multiple thread (SIMT) architecture, the general-purpose graphics compute unit to simultaneously execute the first instruction and the second instruction, wherein the integer operation corresponds to a memory address calculation.

公开(公告)号：US20180300556A1

公开(公告)日：2018-10-18

申请号：US15488555

申请日：2017-04-17

Applicant: Intel Corporation

Inventor： MAYURESH M. VARERKAR ,  BARNAN DAS ,  NARAYAN BISWAL ,  STANLEY J. BARAN ,  GOKCEN CILINGIR ,  NILESH V. SHAH ,  ARCHIE SHARMA ,  SHERINE ABDELHAK ,  SACHIN GODSE ,  FARSHAD AKHBARI ,  NARAYAN SRINIVASA ,  ALTUG KOKER ,  NADATHUR RAJAGOPALAN SATISH ,  DUKHWAN KIM ,  FENG CHEN ,  ABHISHEK R. APPU ,  JOYDEEP RAY ,  PING T. TANG ,  MICHAEL S. STRICKLAND ,  XIAOMING CHEN ,  ANBANG YAO ,  TATIANA SHPEISMAN ,  Vasanth Ranganathan ,  Sanjeev Jahagirdir

IPC: G06K9/00 ,  G06T1/20

CPC classification number: G06K9/00771 ,  G06K9/00362 ,  G06K9/00711 ,  G06K2009/00738 ,  G06T1/20

Abstract: A mechanism is described for facilitating person tracking and data security in machine learning at autonomous machines. A method of embodiments, as described herein, includes detecting, by a camera associated with one or more trackers, a person within a physical vicinity, where detecting includes capturing one or more images the person. The method may further include tracking, by the one or more trackers, the person based on the one or more images of the person, where tracking includes collect tracking data relating to the person. The method may further include selecting a tracker of the one or more trackers as a preferred tracker based on the tracking data.

公开(公告)号：US20180267844A1

公开(公告)日：2018-09-20

申请号：US15537357

申请日：2015-11-24

Applicant: Intel Corporation

Inventor： BRIAN T. LEWIS ,  RAJKISHORE BARIK ,  TATIANA SHPEISMAN

IPC: G06F9/54 ,  G06T1/20

CPC classification number: G06F9/544 ,  G06T1/20

Abstract: Generally, this disclosure provides systems, devices, methods and computer readable media for implementing function callback requests between a first processor (e.g., a GPU) and a second processor (e.g., a CPU). The system may include a shared virtual memory (SVM) coupled to the first and second processors, the SVM configured to store at least one double-ended queue (Deque). An execution unit (EU) of the first processor may be associated with a first of the Deques and configured to push the callback requests to that first Deque. A request handler thread executing on the second processor may be configured to: pop one of the callback requests from the first Deque; execute a function specified by the popped callback request; and generate a completion signal to the EU in response to completion of the function.