公开(公告)号：US20190258533A1

公开(公告)日：2019-08-22

申请号：US16282553

申请日：2019-02-22

Applicant: INTEL CORPORATION

Inventor： BRIAN T. LEWIS ,  RAJKISHORE BARIK ,  TATIANA SHPEISMAN

IPC: G06F9/54 ,  G06T1/20

Abstract: Generally, this disclosure provides systems, devices, methods and computer readable media for implementing function callback requests between a first processor (e.g., a GPU) and a second processor (e.g., a CPU). The system may include a shared virtual memory (SVM) coupled to the first and second processors, the SVM configured to store at least one double-ended queue (Deque). An execution unit (EU) of the first processor may be associated with a first of the Deques and configured to push the callback requests to that first Deque. A request handler thread executing on the second processor may be configured to: pop one of the callback requests from the first Deque; execute a function specified by the popped callback request; and generate a completion signal to the EU in response to completion of the function.

公开(公告)号：US20180300964A1

公开(公告)日：2018-10-18

申请号：US15488914

申请日：2017-04-17

Applicant: Intel Corporation

Inventor： BARATH LAKSHAMANAN ,  LINDA L. HURD ,  BEN J. ASHBAUGH ,  ELMOUSTAPHA OULD-AHMED-VALL ,  LIWEI MA ,  JINGYI JIN ,  JUSTIN E. GOTTSCHLICH ,  CHANDRASEKARAN SAKTHIVEL ,  MICHAEL S. STRICKLAND ,  BRIAN T. LEWIS ,  LINDSEY KUPER ,  ALTUG KOKER ,  ABHISHEK R. APPU ,  PRASOONKUMAR SURTI ,  JOYDEEP RAY ,  BALAJI VEMBU ,  JAVIER S. TUREK ,  NAILA FAROOQUI

IPC: G07C5/00 ,  G05D1/00 ,  G01C21/34 ,  G08G1/052 ,  G08G1/01 ,  H04W28/08 ,  G06N99/00

CPC classification number: G07C5/008 ,  B60W30/00 ,  G01C21/34 ,  G01S19/13 ,  G05D1/0088 ,  G05D2201/0213 ,  G06F9/5027 ,  G06F2209/509 ,  G06N20/00 ,  G08G1/0112 ,  G08G1/012 ,  G08G1/052 ,  H04L43/0852 ,  H04L67/12 ,  H04W28/08

Abstract: One embodiment provides for a computing device within an autonomous vehicle, the compute device comprising a wireless network device to enable a wireless data connection with an autonomous vehicle network, a set of multiple processors including a general-purpose processor and a general-purpose graphics processor, the set of multiple processors to execute a compute manager to manage execution of compute workloads associated with the autonomous vehicle, the compute workload associated with autonomous operations of the autonomous vehicle, and offload logic configured to execute on the set of multiple processors, the offload logic to determine to offload one or more of the compute workloads to one or more autonomous vehicles within range of the wireless network device.

公开(公告)号：US20190318550A1

公开(公告)日：2019-10-17

申请号：US16383849

申请日：2019-04-15

Applicant: Intel Corporation

Inventor： BARATH LAKSHAMANAN ,  LINDA l. HURD ,  BEN J. ASHBAUGH ,  ELMOUSTAPHA OULD-AHMED-VALL ,  LIWEI MA ,  JINGYI JIN ,  JUSTIN E. GOTTSCHLICH ,  CHANDRASEKARAN SAKTHIVEL ,  MICHAEL S. STRICKLAND ,  BRIAN T. LEWIS ,  LINDSEY KUPER ,  ALTUG KOKER ,  ABHISHEK R. APPU ,  PRASOONKUMAR SURTI ,  JOYDEEP RAY ,  BALAJI VEMBU ,  JAVIER S. TUREK ,  NAILA FAROOQUI

IPC: G07C5/00 ,  G06F9/50 ,  H04W28/08 ,  B60W30/00 ,  H04L29/08 ,  G01C21/34 ,  G05D1/00 ,  G08G1/01 ,  G06N20/00

Abstract: One embodiment provides for a computing device within an autonomous vehicle, the compute device comprising a wireless network device to enable a wireless data connection with an autonomous vehicle network, a set of multiple processors including a general-purpose processor and a general-purpose graphics processor, the set of multiple processors to execute a compute manager to manage execution of compute workloads associated with the autonomous vehicle, the compute workload associated with autonomous operations of the autonomous vehicle, and offload logic configured to execute on the set of multiple processors, the offload logic to determine to offload one or more of the compute workloads to one or more autonomous vehicles within range of the wireless network device.

公开(公告)号：US20180267844A1

公开(公告)日：2018-09-20

申请号：US15537357

申请日：2015-11-24

Applicant: Intel Corporation

Inventor： BRIAN T. LEWIS ,  RAJKISHORE BARIK ,  TATIANA SHPEISMAN

IPC: G06F9/54 ,  G06T1/20

CPC classification number: G06F9/544 ,  G06T1/20

Abstract: Generally, this disclosure provides systems, devices, methods and computer readable media for implementing function callback requests between a first processor (e.g., a GPU) and a second processor (e.g., a CPU). The system may include a shared virtual memory (SVM) coupled to the first and second processors, the SVM configured to store at least one double-ended queue (Deque). An execution unit (EU) of the first processor may be associated with a first of the Deques and configured to push the callback requests to that first Deque. A request handler thread executing on the second processor may be configured to: pop one of the callback requests from the first Deque; execute a function specified by the popped callback request; and generate a completion signal to the EU in response to completion of the function.