公开(公告)号：US20180366204A1

公开(公告)日：2018-12-20

申请号：US15627928

申请日：2017-06-20

Applicant: Intel Corporation

Inventor： Ning WU ,  Robert E. FRICKEY

IPC: G11C16/34 ,  G11C16/04

CPC classification number: G11C16/3427 ,  G11C11/34 ,  G11C11/5642 ,  G11C16/0483

Abstract: An apparatus is described. The apparatus includes a storage device having multiple non volatile memory chips and controller circuitry. The controller circuitry is to implement wear leveling of storage cells of the non volatile memory chips at a granularity of segments of storage cell arrays of the non volatile memory chips that share a same disturber node and that are coupled to a same storage cell array wire to diminish disturb errors.

公开(公告)号：US20160379715A1

公开(公告)日：2016-12-29

申请号：US14752817

申请日：2015-06-26

Applicant: INTEL CORPORATION

Inventor： David J. PELSTER ,  Yogesh B. WAKCHAURE ,  Xin GUO ,  Paul D. RUBY ,  Justin R. DAYACAP ,  Joseph F. DOLLER ,  Robert E. FRICKEY

IPC: G11C16/16 ,  G11C16/34 ,  G11C16/26

CPC classification number: G11C16/16 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  G11C16/32 ,  G11C16/3445 ,  G11C2216/20

Abstract: Provided are an apparatus, memory controller and method for performing a block erase operation with respect to a non-volatile memory. A command is generated to perform a portion of the block erase operation. At least one read or write operation is performed after executing the command. An additional instance of the command is executed in response to determining that the block erase operation did not complete after performing the at least one read or write operation.

Abstract translation: 提供了一种用于对非易失性存储器执行块擦除操作的装置，存储器控制器和方法。 产生用于执行块擦除操作的一部分的命令。 在执行命令后至少执行一次读或写操作。 响应于在执行至少一个读或写操作之后确定块擦除操作未完成，执行命令的附加实例。

公开(公告)号：US20190279730A1

公开(公告)日：2019-09-12

申请号：US16357771

申请日：2019-03-19

Applicant: Intel Corporation

Inventor： Ning WU ,  Robert E. FRICKEY

IPC: G11C16/34 ,  G11C16/04

Abstract: An apparatus is described. The apparatus includes a solid state drive having multiple three dimensional stacked FLASH memory chips and controller circuitry. The controller circuitry is to implement wear leveling of storage cells of the FLASH memory chips at a granularity of segments of blocks of said FLASH memory chips that are coupled to a same word line and source gate source node to diminish word line read disturb errors.